A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface

This paper presents a low-power Simultaneous Bidirectional (SBD) transceiver with a power consumption of 0.708 pJ/bit, supporting a 56-Gb/s single-ended high-bandwidth density for die-to-die communication. To address the issue of separating signal amplitude mismatch in the SBD hybrid circuit, a transmitter driver with feed-forward equalization (FFE) is designed to realize adjustable impedance and amplitude. Instead of using a transconductance amplifier (TIA), the R-CTLE circuit is designed to compensate for insertion loss while improving the Signal Integrity (SI). Designed in a 28 nm standard CMOS process, the transceiver demonstrates 56 Gb/s/wire (28 Gb/s each direction) over a 21 mm on-chip channel. The energy efficiency is 0.708 picojoules per bit (0.708 pJ/bit) and a bit error rate (BER) ¡10e−12 with compensating insertion loss of −4.16 dB.