Edge-combining multi-phase DLL frequency multiplier with reduced static phase offset and linearized delay transfer curve

An edge-combining delay-locked loop (ECDLL) frequency multiplier with multi phase outputs is presented. In contrast to architectures based on phase-locked loop, the proposed frequency multiplier produces outputs with 25 % duty cycle without operating at multiple times of the required output frequency. Level of reference spurs at the DLL outputs is reduced by a static phase error suppression technique. In this technique, reset pulse of phase detector (PD) is used to steer charge pump (CP) currents to a dummy branch during idle interval of PD and eliminate CP current mismatch effect. This paper also presents a delay cell with linear transfer curve to increase control range of delay line and provide rather constant loop parameters in a rail-to -rail tuning voltage range. Employing the mentioned techniques, an ECDLL with a frequency multiplication factor of N = 14 and 4-phase outputs has been designed in a 0.18 μm CMOS technology. Post-layout simulation results of the designed ECDLL have been provided in this technology. At 1.4 GHz output frequency, static phase offset simulation result shows a reference spur level reduction of about 18 dB compared to conventional PD/CP circuit. From Monte Carlo simulations, which consider effect of delay mismatch among the delay cells, mean spur level is about −40 dBc. Phase noise analysis, based on a discrete-time (Z-domain) model, for the multiphase ECDLL has been provided and its predictions are close to the simulation results. Phase noise at 10, 100 kHz and 1 MHz frequency offsets is −102.7, −112.5 and −120.1 dBc/Hz, respectively. The circuit consumes 20 mW from a 1.8 V supply.