Design of Fourth-Order Continuous-Time Bandpass ΔΣAD Modulator for RF Sampling
This paper presents the design of a fourth‐order continuous‐time bandpass ΔΣAD modulator for RF sampling. It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been desc...
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| Veröffentlicht in: | IEEJ transactions on electrical and electronic engineering 2010-11, Vol.5 (6), p.639-645 |
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| container_title | IEEJ transactions on electrical and electronic engineering |
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| creator | Lin, Haijun Lo Ré, Pascal Iizuka, Kunihiko Kobayashi, Haruo Takai, Nobukazu |
| description | This paper presents the design of a fourth‐order continuous‐time bandpass ΔΣAD modulator for RF sampling. It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µm CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. |
| doi_str_mv | 10.1002/tee.20586 |
| format | Article |
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It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µm CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.</description><identifier>ISSN: 1931-4973</identifier><identifier>EISSN: 1931-4981</identifier><identifier>DOI: 10.1002/tee.20586</identifier><language>eng</language><publisher>Hoboken: Wiley Subscription Services, Inc., A Wiley Company</publisher><subject>ADC ; Amplifiers ; Applied sciences ; bandpass ; Circuit properties ; Electric, optical and optoelectronic circuits ; Electrical engineering. Electrical power engineering ; Electronic circuits ; Electronic equipment and fabrication. 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It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µm CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.</description><subject>ADC</subject><subject>Amplifiers</subject><subject>Applied sciences</subject><subject>bandpass</subject><subject>Circuit properties</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electrical engineering. Electrical power engineering</subject><subject>Electronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Power electronics, power supplies</subject><subject>RF sampling</subject><subject>Signal convertors</subject><subject>software-defined radio</subject><subject>ΔΣ modulator</subject><issn>1931-4973</issn><issn>1931-4981</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><recordid>eNp1kEFOwzAQRS0EEqWw4AbZsGCR1o6dOFmWtmmRCq2gwNKaOHYJpEllJ4Legxtwn56JQKA7FqOZxftfmofQOcE9grHXr5TqedgPgwPUIRElLotCcri_OT1GJ9a-YMwCGoYdtBgpm60Kp9ROXNamenbnJlXGGZZFlRV1WVt3ma2VcwVFugFrnd3H7nMwcm7KtM6hKo2jm7mLnXtYb_KsWJ2iIw25VWe_u4se4vFyOHVn88n1cDBzJWU8cDl4imvMAYAoFiUkDbWOAhlpooDzMNLg-RAlSgZSMokDAEkTiRPmE2Dap1102fZKU1prlBYbk63BbAXB4luFaFSIHxUNe9GyzQcScm2gkJndBzxKCaUcN1y_5d6yXG3_LxTL8fiv2W0Tma3U-z4B5lUEnHJfPN1ORLwIg2nIhuKRfgHOFH4O</recordid><startdate>201011</startdate><enddate>201011</enddate><creator>Lin, Haijun</creator><creator>Lo Ré, Pascal</creator><creator>Iizuka, Kunihiko</creator><creator>Kobayashi, Haruo</creator><creator>Takai, Nobukazu</creator><general>Wiley Subscription Services, Inc., A Wiley Company</general><general>Wiley</general><scope>BSCLL</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201011</creationdate><title>Design of Fourth-Order Continuous-Time Bandpass ΔΣAD Modulator for RF Sampling</title><author>Lin, Haijun ; Lo Ré, Pascal ; Iizuka, Kunihiko ; Kobayashi, Haruo ; Takai, Nobukazu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3476-7a2e7f07aaa1e49b1d8ff96c9f1ea7789fa25a9bec6cc4c06aac3bc0b451a4f53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>ADC</topic><topic>Amplifiers</topic><topic>Applied sciences</topic><topic>bandpass</topic><topic>Circuit properties</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electrical engineering. Electrical power engineering</topic><topic>Electronic circuits</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Power electronics, power supplies</topic><topic>RF sampling</topic><topic>Signal convertors</topic><topic>software-defined radio</topic><topic>ΔΣ modulator</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lin, Haijun</creatorcontrib><creatorcontrib>Lo Ré, Pascal</creatorcontrib><creatorcontrib>Iizuka, Kunihiko</creatorcontrib><creatorcontrib>Kobayashi, Haruo</creatorcontrib><creatorcontrib>Takai, Nobukazu</creatorcontrib><collection>Istex</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEJ transactions on electrical and electronic engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Lin, Haijun</au><au>Lo Ré, Pascal</au><au>Iizuka, Kunihiko</au><au>Kobayashi, Haruo</au><au>Takai, Nobukazu</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design of Fourth-Order Continuous-Time Bandpass ΔΣAD Modulator for RF Sampling</atitle><jtitle>IEEJ transactions on electrical and electronic engineering</jtitle><addtitle>IEEJ Trans Elec Electron Eng</addtitle><date>2010-11</date><risdate>2010</risdate><volume>5</volume><issue>6</issue><spage>639</spage><epage>645</epage><pages>639-645</pages><issn>1931-4973</issn><eissn>1931-4981</eissn><abstract>This paper presents the design of a fourth‐order continuous‐time bandpass ΔΣAD modulator for RF sampling. It employs subsampling, RF DAC, as well as digital techniques to compensate for finite Q and excess loop delay, and its loop filter uses inverter‐type OTAs; these basic techniques have been described in our previous papers. This paper validates a transistor‐level circuit design of a complete fourth‐order modulator that combines all of the above techniques, and its SPICE simulation results are as follows: the center of the signal band is 2.4 GHz, the sampling frequency is 3.2 GHz, the signal bandwidth is 2 MHz, the peak SNDR is 56 dB, the power consumption from a 1.8‐V supply voltage is 50 mW, and it uses TSMC 0.18‐µm CMOS process. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.</abstract><cop>Hoboken</cop><pub>Wiley Subscription Services, Inc., A Wiley Company</pub><doi>10.1002/tee.20586</doi><tpages>7</tpages></addata></record> |
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| subjects | ADC Amplifiers Applied sciences bandpass Circuit properties Electric, optical and optoelectronic circuits Electrical engineering. Electrical power engineering Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Power electronics, power supplies RF sampling Signal convertors software-defined radio ΔΣ modulator |
| title | Design of Fourth-Order Continuous-Time Bandpass ΔΣAD Modulator for RF Sampling |
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