Low power concurrent compact dual-band receiver front-end using 0.18-μm CMOS process

A fully monolithic dual‐band concurrent receiver front‐end chip for IEEE 802.11a/b/g applications is presented using 0.18‐μm CMOS 1P6M technology. This dual‐band receiver front‐end design uses sub‐harmonic mixer and only one multi‐modulus synthesizer. This low IF circuit design has the advantage of low‐cost and low‐power as comparing with the direct conversion architecture. For a 1.8 V power supply, the overall power consumptions is 66.1 mW. The overall receiver‐chain noise figures are 2.8 dB and 4.3 dB; P1db are −28dBm and −27dBm at 2.45 GHz and 5.25 GHz, and voltage gain is 28.5 dB and 28.1 dB, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1527–1530, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24399