A Novel High‐Speed Ultralow Power Double‐Node‐Upsets Tolerant Automotive Latch Design
This paper introduces a novel High‐speed Ultralow power Double‐Node Upsets (DNU) Tolerant Automotive Latch (HUDTAL) fabricated in the 55‐nm CMOS technology. Through the integration of Muller‐C‐Element (MCE), Node‐Hardened MCE, CLK‐Gating MCE (CG‐MCE), and Transmission Gate techniques, the proposed l...
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Veröffentlicht in: | International journal of circuit theory and applications 2024-12 |
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creator | Qiu, Guoji Bi, Dawei Hu, Zhiyuan Zhang, Zhengxuan |
description | This paper introduces a novel High‐speed Ultralow power Double‐Node Upsets (DNU) Tolerant Automotive Latch (HUDTAL) fabricated in the 55‐nm CMOS technology. Through the integration of Muller‐C‐Element (MCE), Node‐Hardened MCE, CLK‐Gating MCE (CG‐MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions. |
doi_str_mv | 10.1002/cta.4401 |
format | Article |
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Through the integration of Muller‐C‐Element (MCE), Node‐Hardened MCE, CLK‐Gating MCE (CG‐MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. 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Through the integration of Muller‐C‐Element (MCE), Node‐Hardened MCE, CLK‐Gating MCE (CG‐MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions.</abstract><doi>10.1002/cta.4401</doi><orcidid>https://orcid.org/0009-0003-2565-0608</orcidid></addata></record> |
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title | A Novel High‐Speed Ultralow Power Double‐Node‐Upsets Tolerant Automotive Latch Design |
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