High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform

High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform

3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed...

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Hauptverfasser: Lee, Changseob, Kwon, Ikhyeon, Samanta, Anirban, Li, Siwei, Yoo, S. J. Ben
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creator Lee, Changseob
Kwon, Ikhyeon
Samanta, Anirban
Li, Siwei
Yoo, S. J. Ben
description 3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed memory operations are described through the model.
doi_str_mv 10.48550/arxiv.2409.07598
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fullrecord <record><control><sourceid>arxiv_GOX</sourceid><recordid>TN_cdi_arxiv_primary_2409_07598</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2409_07598</sourcerecordid><originalsourceid>FETCH-arxiv_primary_2409_075983</originalsourceid><addsrcrecordid>eNqFjjsLwjAUhbM4iPoDnLx7aRu1xXYUH7iowXYvoaTthTQp1_j692pxdzgcDnxwPsamcx5ESRzzUNIT78Ei4mnAV3GaDNntgHUDQlFlqZWmVJA3pJSfK2rRSP2ZL8KrswSX9REe6BqQILxQhKc-Jw-2tkNTgyBboVZgzYfIUGNpjS8a66zBEjbHcwZCS_c9GrNBJfVVTX49YrP9Lt8c_F6w6AhbSa_iK1r0osv_xBsnRUdZ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform</title><source>arXiv.org</source><creator>Lee, Changseob ; Kwon, Ikhyeon ; Samanta, Anirban ; Li, Siwei ; Yoo, S. J. Ben</creator><creatorcontrib>Lee, Changseob ; Kwon, Ikhyeon ; Samanta, Anirban ; Li, Siwei ; Yoo, S. J. Ben</creatorcontrib><description>3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed memory operations are described through the model.</description><identifier>DOI: 10.48550/arxiv.2409.07598</identifier><language>eng</language><subject>Computer Science - Systems and Control</subject><creationdate>2024-09</creationdate><rights>http://creativecommons.org/licenses/by/4.0</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>228,230,776,881</link.rule.ids><linktorsrc>$$Uhttps://arxiv.org/abs/2409.07598$$EView_record_in_Cornell_University$$FView_record_in_$$GCornell_University$$Hfree_for_read</linktorsrc><backlink>$$Uhttps://doi.org/10.48550/arXiv.2409.07598$$DView paper in arXiv$$Hfree_for_read</backlink></links><search><creatorcontrib>Lee, Changseob</creatorcontrib><creatorcontrib>Kwon, Ikhyeon</creatorcontrib><creatorcontrib>Samanta, Anirban</creatorcontrib><creatorcontrib>Li, Siwei</creatorcontrib><creatorcontrib>Yoo, S. J. Ben</creatorcontrib><title>High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform</title><description>3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed memory operations are described through the model.</description><subject>Computer Science - Systems and Control</subject><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>GOX</sourceid><recordid>eNqFjjsLwjAUhbM4iPoDnLx7aRu1xXYUH7iowXYvoaTthTQp1_j692pxdzgcDnxwPsamcx5ESRzzUNIT78Ei4mnAV3GaDNntgHUDQlFlqZWmVJA3pJSfK2rRSP2ZL8KrswSX9REe6BqQILxQhKc-Jw-2tkNTgyBboVZgzYfIUGNpjS8a66zBEjbHcwZCS_c9GrNBJfVVTX49YrP9Lt8c_F6w6AhbSa_iK1r0osv_xBsnRUdZ</recordid><startdate>20240911</startdate><enddate>20240911</enddate><creator>Lee, Changseob</creator><creator>Kwon, Ikhyeon</creator><creator>Samanta, Anirban</creator><creator>Li, Siwei</creator><creator>Yoo, S. J. Ben</creator><scope>AKY</scope><scope>GOX</scope></search><sort><creationdate>20240911</creationdate><title>High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform</title><author>Lee, Changseob ; Kwon, Ikhyeon ; Samanta, Anirban ; Li, Siwei ; Yoo, S. J. Ben</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-arxiv_primary_2409_075983</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Computer Science - Systems and Control</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Changseob</creatorcontrib><creatorcontrib>Kwon, Ikhyeon</creatorcontrib><creatorcontrib>Samanta, Anirban</creatorcontrib><creatorcontrib>Li, Siwei</creatorcontrib><creatorcontrib>Yoo, S. J. Ben</creatorcontrib><collection>arXiv Computer Science</collection><collection>arXiv.org</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Changseob</au><au>Kwon, Ikhyeon</au><au>Samanta, Anirban</au><au>Li, Siwei</au><au>Yoo, S. J. Ben</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform</atitle><date>2024-09-11</date><risdate>2024</risdate><abstract>3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional structure (PNPN). TCAD is used to reflect the physical behavior, and the high-speed memory operations are described through the model.</abstract><doi>10.48550/arxiv.2409.07598</doi><oa>free_for_read</oa></addata></record>
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title High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T19%3A07%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-arxiv_GOX&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=High%20Performance%20Three-Terminal%20Thyristor%20RAM%20with%20a%20P+/P/N/P/N/N+%20Doping%20Profile%20on%20a%20Silicon-Photonic%20CMOS%20Platform&rft.au=Lee,%20Changseob&rft.date=2024-09-11&rft_id=info:doi/10.48550/arxiv.2409.07598&rft_dat=%3Carxiv_GOX%3E2409_07598%3C/arxiv_GOX%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true