Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predicting the data value of a load instruction. Howeve...

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Hauptverfasser:	Bera, Rahul, Ranganathan, Adithya, Rakshit, Joydeep, Mahto, Sujit, Nori, Anant V, Gaur, Jayesh, Olgun, Ataberk, Kanellopoulos, Konstantinos, Sadrosadati, Mohammad, Subramoney, Sreenivas, Mutlu, Onur
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer Science - Hardware Architecture
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