Low-power In-pixel Computing with Current-modulated Switched Capacitors

We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend. Unlike the state-of-the-art (SOA) analog process-in-pixel (PIP) that modulates the exposure time of photosensors when performing matrix-...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Zhang, David, van der Wal, Gooitzen, Farkya, Saurabh, Senko, Thomas, Raghavan, Aswin, Isnardi, Michael, Piacentino, Michael
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer Science - Hardware Architecture
Online-Zugang:	Volltext bestellen
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