The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing
This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level,...
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| creator | Höppner, Sebastian Yan, Yexin Dixius, Andreas Scholze, Stefan Partzsch, Johannes Stolba, Marco Kelber, Florian Vogginger, Bernhard Neumärker, Felix Ellguth, Georg Hartmann, Stephan Schiefer, Stefan Hocker, Thomas Walter, Dennis Liu, Genting Garside, Jim Furber, Steve Mayr, Christian |
| description | This paper introduces the processing element architecture of the second
generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the
chip features adaptive body biasing for near-threshold operation, and dynamic
voltage-and-frequency scaling driven by spiking activity. On system level,
processing is centered around an ARM M4 core, similar to the processor-centric
architecture of the first generation SpiNNaker. To speed operation of subtasks,
we have added accelerators for numerical operations of both spiking (SNN) and
rate based (deep) neural networks (DNN). PEs communicate via a dedicated,
custom-designed network-on-chip. We present three benchmarks showing operation
of the whole processor element on SNN, DNN and hybrid SNN/DNN networks. |
| doi_str_mv | 10.48550/arxiv.2103.08392 |
| format | Article |
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generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the
chip features adaptive body biasing for near-threshold operation, and dynamic
voltage-and-frequency scaling driven by spiking activity. On system level,
processing is centered around an ARM M4 core, similar to the processor-centric
architecture of the first generation SpiNNaker. To speed operation of subtasks,
we have added accelerators for numerical operations of both spiking (SNN) and
rate based (deep) neural networks (DNN). PEs communicate via a dedicated,
custom-designed network-on-chip. We present three benchmarks showing operation
of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.</description><identifier>DOI: 10.48550/arxiv.2103.08392</identifier><language>eng</language><subject>Computer Science - Hardware Architecture</subject><creationdate>2021-03</creationdate><rights>http://creativecommons.org/licenses/by/4.0</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-a1632-48ab44af35559130a1399bd89826447cf70228d1656ed679b4017cb28ad573d53</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>228,230,776,881</link.rule.ids><linktorsrc>$$Uhttps://arxiv.org/abs/2103.08392$$EView_record_in_Cornell_University$$FView_record_in_$$GCornell_University$$Hfree_for_read</linktorsrc><backlink>$$Uhttps://doi.org/10.48550/arXiv.2103.08392$$DView paper in arXiv$$Hfree_for_read</backlink></links><search><creatorcontrib>Höppner, Sebastian</creatorcontrib><creatorcontrib>Yan, Yexin</creatorcontrib><creatorcontrib>Dixius, Andreas</creatorcontrib><creatorcontrib>Scholze, Stefan</creatorcontrib><creatorcontrib>Partzsch, Johannes</creatorcontrib><creatorcontrib>Stolba, Marco</creatorcontrib><creatorcontrib>Kelber, Florian</creatorcontrib><creatorcontrib>Vogginger, Bernhard</creatorcontrib><creatorcontrib>Neumärker, Felix</creatorcontrib><creatorcontrib>Ellguth, Georg</creatorcontrib><creatorcontrib>Hartmann, Stephan</creatorcontrib><creatorcontrib>Schiefer, Stefan</creatorcontrib><creatorcontrib>Hocker, Thomas</creatorcontrib><creatorcontrib>Walter, Dennis</creatorcontrib><creatorcontrib>Liu, Genting</creatorcontrib><creatorcontrib>Garside, Jim</creatorcontrib><creatorcontrib>Furber, Steve</creatorcontrib><creatorcontrib>Mayr, Christian</creatorcontrib><title>The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing</title><description>This paper introduces the processing element architecture of the second
generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the
chip features adaptive body biasing for near-threshold operation, and dynamic
voltage-and-frequency scaling driven by spiking activity. On system level,
processing is centered around an ARM M4 core, similar to the processor-centric
architecture of the first generation SpiNNaker. To speed operation of subtasks,
we have added accelerators for numerical operations of both spiking (SNN) and
rate based (deep) neural networks (DNN). PEs communicate via a dedicated,
custom-designed network-on-chip. We present three benchmarks showing operation
of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.</description><subject>Computer Science - Hardware Architecture</subject><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>GOX</sourceid><recordid>eNotz71OwzAYhWEvDKhwAUz4BhL8G9tjFQpFqgISZWCK_JfGImmiLwmidw8UpjO9R3oQuqEkF1pKcmfhK33mjBKeE80Nu0Tv-zbi1zFVlf2IgBl-gcHHaUrHA950sY_HGa_Bt2mOfl4g4mYAvD05SAHfp0OabYeruMDQDzC2yeNy6Mdl_smv0EVjuyle_-8KvT1s9uU22z0_PpXrXWZpwVkmtHVC2IZLKQ3lxFJujAvaaFYIoXyjCGM60EIWMRTKOEGo8o5pG6TiQfIVuv37PePqEVJv4VT_Iuszkn8DGpBL1w</recordid><startdate>20210315</startdate><enddate>20210315</enddate><creator>Höppner, Sebastian</creator><creator>Yan, Yexin</creator><creator>Dixius, Andreas</creator><creator>Scholze, Stefan</creator><creator>Partzsch, Johannes</creator><creator>Stolba, Marco</creator><creator>Kelber, Florian</creator><creator>Vogginger, Bernhard</creator><creator>Neumärker, Felix</creator><creator>Ellguth, Georg</creator><creator>Hartmann, Stephan</creator><creator>Schiefer, Stefan</creator><creator>Hocker, Thomas</creator><creator>Walter, Dennis</creator><creator>Liu, Genting</creator><creator>Garside, Jim</creator><creator>Furber, Steve</creator><creator>Mayr, Christian</creator><scope>AKY</scope><scope>GOX</scope></search><sort><creationdate>20210315</creationdate><title>The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing</title><author>Höppner, Sebastian ; Yan, Yexin ; Dixius, Andreas ; Scholze, Stefan ; Partzsch, Johannes ; Stolba, Marco ; Kelber, Florian ; Vogginger, Bernhard ; Neumärker, Felix ; Ellguth, Georg ; Hartmann, Stephan ; Schiefer, Stefan ; Hocker, Thomas ; Walter, Dennis ; Liu, Genting ; Garside, Jim ; Furber, Steve ; Mayr, Christian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a1632-48ab44af35559130a1399bd89826447cf70228d1656ed679b4017cb28ad573d53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Computer Science - Hardware Architecture</topic><toplevel>online_resources</toplevel><creatorcontrib>Höppner, Sebastian</creatorcontrib><creatorcontrib>Yan, Yexin</creatorcontrib><creatorcontrib>Dixius, Andreas</creatorcontrib><creatorcontrib>Scholze, Stefan</creatorcontrib><creatorcontrib>Partzsch, Johannes</creatorcontrib><creatorcontrib>Stolba, Marco</creatorcontrib><creatorcontrib>Kelber, Florian</creatorcontrib><creatorcontrib>Vogginger, Bernhard</creatorcontrib><creatorcontrib>Neumärker, Felix</creatorcontrib><creatorcontrib>Ellguth, Georg</creatorcontrib><creatorcontrib>Hartmann, Stephan</creatorcontrib><creatorcontrib>Schiefer, Stefan</creatorcontrib><creatorcontrib>Hocker, Thomas</creatorcontrib><creatorcontrib>Walter, Dennis</creatorcontrib><creatorcontrib>Liu, Genting</creatorcontrib><creatorcontrib>Garside, Jim</creatorcontrib><creatorcontrib>Furber, Steve</creatorcontrib><creatorcontrib>Mayr, Christian</creatorcontrib><collection>arXiv Computer Science</collection><collection>arXiv.org</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Höppner, Sebastian</au><au>Yan, Yexin</au><au>Dixius, Andreas</au><au>Scholze, Stefan</au><au>Partzsch, Johannes</au><au>Stolba, Marco</au><au>Kelber, Florian</au><au>Vogginger, Bernhard</au><au>Neumärker, Felix</au><au>Ellguth, Georg</au><au>Hartmann, Stephan</au><au>Schiefer, Stefan</au><au>Hocker, Thomas</au><au>Walter, Dennis</au><au>Liu, Genting</au><au>Garside, Jim</au><au>Furber, Steve</au><au>Mayr, Christian</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing</atitle><date>2021-03-15</date><risdate>2021</risdate><abstract>This paper introduces the processing element architecture of the second
generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the
chip features adaptive body biasing for near-threshold operation, and dynamic
voltage-and-frequency scaling driven by spiking activity. On system level,
processing is centered around an ARM M4 core, similar to the processor-centric
architecture of the first generation SpiNNaker. To speed operation of subtasks,
we have added accelerators for numerical operations of both spiking (SNN) and
rate based (deep) neural networks (DNN). PEs communicate via a dedicated,
custom-designed network-on-chip. We present three benchmarks showing operation
of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.</abstract><doi>10.48550/arxiv.2103.08392</doi><oa>free_for_read</oa></addata></record> |
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| title | The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing |
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