SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment
A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates...
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creator | Kishishita, Tetsuichi Sato, Yutaro Fujita, Yoichi Hamada, Eitaro Mibe, Tsutomu Nagasawa, Tsubasa Shirabe, Shohei Shoji, Masayoshi Suehara, Taikan Tanaka, Manobu M Tojo, Junji Tsutumi, Yuki Yamanaka, Takashi Yoshioka, Tamaki |
description | A new silicon-strip readout chip named "SliT" has been developed for the
measurement of the muon anomalous magnetic moment and electric dipole moment at
J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with
mixed-signal integrated circuits. An analog circuit incorporates a conventional
charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators
for each of 128 identical channels. A digital part includes storage memories,
an event building block, a serializer, and LVDS drivers. A distinct feature of
the SliT is utilization of the zero-cross architecture, which consists of a
CR-RC filter followed by a CR circuit as a voltage differentiator. This
architecture enables to generate hit signals with subnanosecond
amplitude-independent time walk, which is the primary requirement for the
experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between
0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$
(rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other
functionalities such as a strip-sensor readout chip have also been proven in
the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM
experiment. |
doi_str_mv | 10.48550/arxiv.2006.08095 |
format | Article |
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measurement of the muon anomalous magnetic moment and electric dipole moment at
J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with
mixed-signal integrated circuits. An analog circuit incorporates a conventional
charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators
for each of 128 identical channels. A digital part includes storage memories,
an event building block, a serializer, and LVDS drivers. A distinct feature of
the SliT is utilization of the zero-cross architecture, which consists of a
CR-RC filter followed by a CR circuit as a voltage differentiator. This
architecture enables to generate hit signals with subnanosecond
amplitude-independent time walk, which is the primary requirement for the
experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between
0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$
(rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other
functionalities such as a strip-sensor readout chip have also been proven in
the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM
experiment.</description><identifier>DOI: 10.48550/arxiv.2006.08095</identifier><language>eng</language><subject>Physics - High Energy Physics - Experiment ; Physics - Instrumentation and Detectors</subject><creationdate>2020-06</creationdate><rights>http://arxiv.org/licenses/nonexclusive-distrib/1.0</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>228,230,776,881</link.rule.ids><linktorsrc>$$Uhttps://arxiv.org/abs/2006.08095$$EView_record_in_Cornell_University$$FView_record_in_$$GCornell_University$$Hfree_for_read</linktorsrc><backlink>$$Uhttps://doi.org/10.48550/arXiv.2006.08095$$DView paper in arXiv$$Hfree_for_read</backlink><backlink>$$Uhttps://doi.org/10.1109/TNS.2020.3012924$$DView published paper (Access to full text may be restricted)$$Hfree_for_read</backlink></links><search><creatorcontrib>Kishishita, Tetsuichi</creatorcontrib><creatorcontrib>Sato, Yutaro</creatorcontrib><creatorcontrib>Fujita, Yoichi</creatorcontrib><creatorcontrib>Hamada, Eitaro</creatorcontrib><creatorcontrib>Mibe, Tsutomu</creatorcontrib><creatorcontrib>Nagasawa, Tsubasa</creatorcontrib><creatorcontrib>Shirabe, Shohei</creatorcontrib><creatorcontrib>Shoji, Masayoshi</creatorcontrib><creatorcontrib>Suehara, Taikan</creatorcontrib><creatorcontrib>Tanaka, Manobu M</creatorcontrib><creatorcontrib>Tojo, Junji</creatorcontrib><creatorcontrib>Tsutumi, Yuki</creatorcontrib><creatorcontrib>Yamanaka, Takashi</creatorcontrib><creatorcontrib>Yoshioka, Tamaki</creatorcontrib><title>SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment</title><description>A new silicon-strip readout chip named "SliT" has been developed for the
measurement of the muon anomalous magnetic moment and electric dipole moment at
J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with
mixed-signal integrated circuits. An analog circuit incorporates a conventional
charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators
for each of 128 identical channels. A digital part includes storage memories,
an event building block, a serializer, and LVDS drivers. A distinct feature of
the SliT is utilization of the zero-cross architecture, which consists of a
CR-RC filter followed by a CR circuit as a voltage differentiator. This
architecture enables to generate hit signals with subnanosecond
amplitude-independent time walk, which is the primary requirement for the
experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between
0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$
(rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other
functionalities such as a strip-sensor readout chip have also been proven in
the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM
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measurement of the muon anomalous magnetic moment and electric dipole moment at
J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with
mixed-signal integrated circuits. An analog circuit incorporates a conventional
charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators
for each of 128 identical channels. A digital part includes storage memories,
an event building block, a serializer, and LVDS drivers. A distinct feature of
the SliT is utilization of the zero-cross architecture, which consists of a
CR-RC filter followed by a CR circuit as a voltage differentiator. This
architecture enables to generate hit signals with subnanosecond
amplitude-independent time walk, which is the primary requirement for the
experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between
0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$
(rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other
functionalities such as a strip-sensor readout chip have also been proven in
the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM
experiment.</abstract><doi>10.48550/arxiv.2006.08095</doi><oa>free_for_read</oa></addata></record> |
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subjects | Physics - High Energy Physics - Experiment Physics - Instrumentation and Detectors |
title | SliT: A Strip-sensor Readout Chip with Subnanosecond Time-walk for the J-PARC Muon $g-2$/EDM Experiment |
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