Mixed-level identification of fault redundancy in microprocessors

A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the instruction set, and is specified as a set of data constraints to be satisfied by test data generation. We show that the high-level test, which sati...

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Veröffentlicht in:	arXiv.org 2019-07
Hauptverfasser:	Adeboye, Stephen Oyeniran, Ubar, Raimund, Jenihhin, Maksim, Gursoy, Cemil Cem, Raik, Jaan
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer Science - Hardware Architecture Computer simulation Constraint modelling Fault detection Low level Microprocessors Redundancy Test procedures
Online-Zugang:	Volltext
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