Voltage Controlled Memristor Threshold Logic Gates

In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic i...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Maan, Akshay Kumar, James, Alex Pappachen
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer Science - Emerging Technologies
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Maan, Akshay Kumar James, Alex Pappachen
description	In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.
doi_str_mv	10.48550/arxiv.1609.04919
format	Article
fullrecord	<record><control><sourceid>arxiv_GOX</sourceid><recordid>TN_cdi_arxiv_primary_1609_04919</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>1609_04919</sourcerecordid><originalsourceid>FETCH-LOGICAL-a679-1fb382fd91c85e70608f5dda9c088d54c17d89f2223c1fe010b44f13dee597b53</originalsourceid><addsrcrecordid>eNotzr1OwzAUQGEvHVDhAZjwCyTc65_EHlEEBSmIJWKNHPu6jeTiyolQ-_aIwnS2o4-xe4RaGa3h0ZXz_F1jA7YGZdHeMPGZ0-r2xLv8tZacEgX-TscyL2sufDgUWg45Bd7n_ez5zq203LJNdGmhu_9u2fDyPHSvVf-xe-ue-so1ra0wTtKIGCx6o6mFBkzUITjrwZiglcc2GBuFENJjJECYlIooA5G27aTllj38ba_o8VTmoyuX8Rc_XvHyB9oHPrE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Voltage Controlled Memristor Threshold Logic Gates</title><source>arXiv.org</source><creator>Maan, Akshay Kumar ; James, Alex Pappachen</creator><creatorcontrib>Maan, Akshay Kumar ; James, Alex Pappachen</creatorcontrib><description>In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.</description><identifier>DOI: 10.48550/arxiv.1609.04919</identifier><language>eng</language><subject>Computer Science - Emerging Technologies</subject><creationdate>2016-09</creationdate><rights>http://arxiv.org/licenses/nonexclusive-distrib/1.0</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>228,230,776,881</link.rule.ids><linktorsrc>$$Uhttps://arxiv.org/abs/1609.04919$$EView_record_in_Cornell_University$$FView_record_in_$$GCornell_University$$Hfree_for_read</linktorsrc><backlink>$$Uhttps://doi.org/10.48550/arXiv.1609.04919$$DView paper in arXiv$$Hfree_for_read</backlink></links><search><creatorcontrib>Maan, Akshay Kumar</creatorcontrib><creatorcontrib>James, Alex Pappachen</creatorcontrib><title>Voltage Controlled Memristor Threshold Logic Gates</title><description>In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.</description><subject>Computer Science - Emerging Technologies</subject><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>GOX</sourceid><recordid>eNotzr1OwzAUQGEvHVDhAZjwCyTc65_EHlEEBSmIJWKNHPu6jeTiyolQ-_aIwnS2o4-xe4RaGa3h0ZXz_F1jA7YGZdHeMPGZ0-r2xLv8tZacEgX-TscyL2sufDgUWg45Bd7n_ez5zq203LJNdGmhu_9u2fDyPHSvVf-xe-ue-so1ra0wTtKIGCx6o6mFBkzUITjrwZiglcc2GBuFENJjJECYlIooA5G27aTllj38ba_o8VTmoyuX8Rc_XvHyB9oHPrE</recordid><startdate>20160916</startdate><enddate>20160916</enddate><creator>Maan, Akshay Kumar</creator><creator>James, Alex Pappachen</creator><scope>AKY</scope><scope>GOX</scope></search><sort><creationdate>20160916</creationdate><title>Voltage Controlled Memristor Threshold Logic Gates</title><author>Maan, Akshay Kumar ; James, Alex Pappachen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a679-1fb382fd91c85e70608f5dda9c088d54c17d89f2223c1fe010b44f13dee597b53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Computer Science - Emerging Technologies</topic><toplevel>online_resources</toplevel><creatorcontrib>Maan, Akshay Kumar</creatorcontrib><creatorcontrib>James, Alex Pappachen</creatorcontrib><collection>arXiv Computer Science</collection><collection>arXiv.org</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Maan, Akshay Kumar</au><au>James, Alex Pappachen</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Voltage Controlled Memristor Threshold Logic Gates</atitle><date>2016-09-16</date><risdate>2016</risdate><abstract>In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.</abstract><doi>10.48550/arxiv.1609.04919</doi><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier	DOI: 10.48550/arxiv.1609.04919
ispartof
issn
language	eng
recordid	cdi_arxiv_primary_1609_04919
source	arXiv.org
subjects	Computer Science - Emerging Technologies
title	Voltage Controlled Memristor Threshold Logic Gates
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T19%3A27%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-arxiv_GOX&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Voltage%20Controlled%20Memristor%20Threshold%20Logic%20Gates&rft.au=Maan,%20Akshay%20Kumar&rft.date=2016-09-16&rft_id=info:doi/10.48550/arxiv.1609.04919&rft_dat=%3Carxiv_GOX%3E1609_04919%3C/arxiv_GOX%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true