Robustness against Power is PSPACE-complete

Power is a RISC architecture developed by IBM, Freescale, and several other companies and implemented in a series of POWER processors. The architecture features a relaxed memory model providing very weak guarantees with respect to the ordering and atomicity of memory accesses. Due to these weaknesse...

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Bibliographische Detailangaben

Hauptverfasser:	Derevenetc, Egor, Meyer, Roland
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer Science - Logic in Computer Science
Online-Zugang:	Volltext bestellen
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