Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Dans Design, Automation and Test in Europe | Designers'Forum - DATE'05, Munich : Allemagne (2005) The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC)....
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| creator | Mayer, A Siebert, H Mcdonald-Maier, K. D |
| description | Dans Design, Automation and Test in Europe | Designers'Forum -
DATE'05, Munich : Allemagne (2005) The introduction of complex SoCs with multiple processor cores presents new
development challenges, such that development support is now a decisive factor
when choosing a System-on-Chip (SoC). The presented developments support
strategy addresses the challenges using both architecture and technology
approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible
triggering using cross triggers and a multiple core break and suspend switch.
Temporal trace ordering is guaranteed down to cycle level by on-chip time
stamping. The Package Sized-ICE (PSI) approach is a novel method of including
trace buffers, overlay memories, processing resources and communication
interfaces without changing device behavior. PSI requires no external emulation
box, as the debug host interfaces directly with the SoC using a standard
interface. |
| doi_str_mv | 10.48550/arxiv.0710.4827 |
| format | Article |
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DATE'05, Munich : Allemagne (2005) The introduction of complex SoCs with multiple processor cores presents new
development challenges, such that development support is now a decisive factor
when choosing a System-on-Chip (SoC). The presented developments support
strategy addresses the challenges using both architecture and technology
approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible
triggering using cross triggers and a multiple core break and suspend switch.
Temporal trace ordering is guaranteed down to cycle level by on-chip time
stamping. The Package Sized-ICE (PSI) approach is a novel method of including
trace buffers, overlay memories, processing resources and communication
interfaces without changing device behavior. PSI requires no external emulation
box, as the debug host interfaces directly with the SoC using a standard
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DATE'05, Munich : Allemagne (2005) The introduction of complex SoCs with multiple processor cores presents new
development challenges, such that development support is now a decisive factor
when choosing a System-on-Chip (SoC). The presented developments support
strategy addresses the challenges using both architecture and technology
approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible
triggering using cross triggers and a multiple core break and suspend switch.
Temporal trace ordering is guaranteed down to cycle level by on-chip time
stamping. The Package Sized-ICE (PSI) approach is a novel method of including
trace buffers, overlay memories, processing resources and communication
interfaces without changing device behavior. PSI requires no external emulation
box, as the debug host interfaces directly with the SoC using a standard
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DATE'05, Munich : Allemagne (2005) The introduction of complex SoCs with multiple processor cores presents new
development challenges, such that development support is now a decisive factor
when choosing a System-on-Chip (SoC). The presented developments support
strategy addresses the challenges using both architecture and technology
approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible
triggering using cross triggers and a multiple core break and suspend switch.
Temporal trace ordering is guaranteed down to cycle level by on-chip time
stamping. The Package Sized-ICE (PSI) approach is a novel method of including
trace buffers, overlay memories, processing resources and communication
interfaces without changing device behavior. PSI requires no external emulation
box, as the debug host interfaces directly with the SoC using a standard
interface.</abstract><doi>10.48550/arxiv.0710.4827</doi><oa>free_for_read</oa></addata></record> |
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| identifier | DOI: 10.48550/arxiv.0710.4827 |
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| language | eng |
| recordid | cdi_arxiv_primary_0710_4827 |
| source | arXiv.org |
| subjects | Computer Science - Hardware Architecture |
| title | Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs |
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