Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty...
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| creator | Mesman, Bart Pinto, Carlos A. Alba Koen Van Eijk |
| description | Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in this paper analyses the combination of limited register file capacity, resource- and timing constraints during scheduling. Value lifetimes are serialized until all capacity constraints are guaranteed to be satisfied after scheduling. Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for inner-most loops of DSP algorithms. |
| doi_str_mv | 10.5555/857198.857953 |
| format | Conference Proceeding |
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Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for inner-most loops of DSP algorithms.</description><identifier>ISBN: 076950356X</identifier><identifier>ISBN: 9780769503561</identifier><identifier>DOI: 10.5555/857198.857953</identifier><language>eng</language><publisher>Washington, DC, USA: IEEE Computer Society</publisher><subject>Theory of computation ; Theory of computation -- Design and analysis of algorithms ; Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis ; Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms ; Theory of computation -- Theory and algorithms for application domains ; Theory of computation -- Theory and algorithms for application domains -- Machine learning theory ; Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning ; Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making</subject><ispartof>12th International Symposium on System Synthesis : November 10-12, 1999, San Jose, California : proceedings, 1999, p.100-100</ispartof><rights>Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. 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| identifier | ISBN: 076950356X |
| ispartof | 12th International Symposium on System Synthesis : November 10-12, 1999, San Jose, California : proceedings, 1999, p.100-100 |
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| language | eng |
| recordid | cdi_acm_books_10_5555_857198_857953 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Theory of computation Theory of computation -- Design and analysis of algorithms Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis Theory of computation -- Design and analysis of algorithms -- Approximation algorithms analysis -- Scheduling algorithms Theory of computation -- Theory and algorithms for application domains Theory of computation -- Theory and algorithms for application domains -- Machine learning theory Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning Theory of computation -- Theory and algorithms for application domains -- Machine learning theory -- Reinforcement learning -- Sequential decision making |
| title | Efficient Scheduling of DSP Code on Processors with Distributed Register Files |
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