Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case

Testing different modules of an integrated circuit concurrently is an efficient way to reduce the total test time. This paper presents a procedure to optimize the parallel test plan to test all functional units present in a data path. Our algorithm defines which registers will be transformed into te...

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Bibliographische Detailangaben

Hauptverfasser:	Amazonas, José Roberto de A., Strum, Marius, Chau, Wang Jiang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Hardware Hardware > Hardware test Hardware > Integrated circuits Hardware > Robustness Hardware > Very large scale integration design
Online-Zugang:	Volltext
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