A model for system-level timed analysis and profiling

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Hauptverfasser:	Allara, A., Fornaciari, W., Salice, F., Sciuto, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied computing > Physical sciences and engineering > Engineering Computing methodologies > Modeling and simulation Hardware > Hardware validation > Functional verification > Simulation and emulation
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creator	Allara, A. Fornaciari, W. Salice, F. Sciuto, D.
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doi_str_mv	10.5555/368058.368134
format	Conference Proceeding
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identifier	ISBN: 9780818683596
ispartof	Design, automation, and test in Europe : proceedings, February 23-26, 1998, Paris, France, 1998, p.204-210
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language	eng
recordid	cdi_acm_books_10_5555_368058_368134
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Applied computing -- Physical sciences and engineering -- Engineering Computing methodologies -- Modeling and simulation Hardware -- Hardware validation -- Functional verification -- Simulation and emulation
title	A model for system-level timed analysis and profiling
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