DATAPATH: a CMOS data path silicon assembler
As an integration of automatic silicon assembly and simulation tools, the DATAPATH Silicon Assembler produces mask geometries and netlists from input specifications written in a Hardware Description Language, MADL. DATAPATH consists of a library of data path cells (i.e. registers, bus prechargers, d...
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| creator | Marshburn, Tom Lui, Ivy Brown, Rick Cheung, Dan Lum, Gary Cheng, Peter |
| description | As an integration of automatic silicon assembly and simulation tools, the DATAPATH Silicon Assembler produces mask geometries and netlists from input specifications written in a Hardware Description Language, MADL. DATAPATH consists of a library of data path cells (i.e. registers, bus prechargers, drivers, interconnects, ALU's and other logic elements) in a flexible bus architecture. The cells are highly parameterized and procedurally described in a hierarchical manner. The layout is automatically generated using a LISP-embedded procedural description language, ICPL, and is independent of design rule changes as a result of parameterization. This paper describes the DATAPATH Silicon Assembler synthesis process which includes the users' interface, the automatic layout generation, the architecture, library and the verification process, all in a single engineering workstation system. |
| doi_str_mv | 10.5555/318013.318149 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>proquest_acm_b</sourceid><recordid>TN_cdi_acm_books_10_5555_318013_318149</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>31174185</sourcerecordid><originalsourceid>FETCH-LOGICAL-a995-4613c785290f58292537d854004066fa68e10d5124202dfa28605909e1ebbd973</originalsourceid><addsrcrecordid>eNqNj0tLAzEUhQMiVGuX_QuunHrvTW4ey6E-KhR0MfuQmUmgdepoY_-_kRHc9mzO5uMcPiGWCCsuuZdoAeWqFCp3Ia7BotVggHgmFjnvAQCRgJGuxOyhbuq3utnciMsUhhwXfz0XzdNjs95U29fnl3W9rYJzXCmNsjOWyUFiS45Ymt6yAlCgdQraRoS-LCsC6lOgcswOXMTYtr0zci5up9nP4_h1ivnbH3a5i8MQPuJ4yl4iGoWW_8HQHXw7ju_ZI_hfPz_5-cmvgHdngb497mKSPwnSStU</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>31174185</pqid></control><display><type>conference_proceeding</type><title>DATAPATH: a CMOS data path silicon assembler</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Marshburn, Tom ; Lui, Ivy ; Brown, Rick ; Cheung, Dan ; Lum, Gary ; Cheng, Peter</creator><creatorcontrib>Marshburn, Tom ; Lui, Ivy ; Brown, Rick ; Cheung, Dan ; Lum, Gary ; Cheng, Peter</creatorcontrib><description>As an integration of automatic silicon assembly and simulation tools, the DATAPATH Silicon Assembler produces mask geometries and netlists from input specifications written in a Hardware Description Language, MADL. DATAPATH consists of a library of data path cells (i.e. registers, bus prechargers, drivers, interconnects, ALU's and other logic elements) in a flexible bus architecture. The cells are highly parameterized and procedurally described in a hierarchical manner. The layout is automatically generated using a LISP-embedded procedural description language, ICPL, and is independent of design rule changes as a result of parameterization. This paper describes the DATAPATH Silicon Assembler synthesis process which includes the users' interface, the automatic layout generation, the architecture, library and the verification process, all in a single engineering workstation system.</description><identifier>ISBN: 0818607025</identifier><identifier>ISBN: 9780818607028</identifier><identifier>DOI: 10.5555/318013.318149</identifier><language>eng</language><publisher>Piscataway, NJ, USA: IEEE Press</publisher><subject>Applied computing -- Physical sciences and engineering -- Engineering ; Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization ; Hardware -- Electronic design automation -- Physical design (EDA) ; Hardware -- Robustness ; Hardware -- Very large scale integration design</subject><ispartof>Proceedings of the 23rd ACM/IEEE Design Automation Conference, 1986, p.722-729</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>309,310,777,781,786,787,27906</link.rule.ids></links><search><creatorcontrib>Marshburn, Tom</creatorcontrib><creatorcontrib>Lui, Ivy</creatorcontrib><creatorcontrib>Brown, Rick</creatorcontrib><creatorcontrib>Cheung, Dan</creatorcontrib><creatorcontrib>Lum, Gary</creatorcontrib><creatorcontrib>Cheng, Peter</creatorcontrib><title>DATAPATH: a CMOS data path silicon assembler</title><title>Proceedings of the 23rd ACM/IEEE Design Automation Conference</title><description>As an integration of automatic silicon assembly and simulation tools, the DATAPATH Silicon Assembler produces mask geometries and netlists from input specifications written in a Hardware Description Language, MADL. DATAPATH consists of a library of data path cells (i.e. registers, bus prechargers, drivers, interconnects, ALU's and other logic elements) in a flexible bus architecture. The cells are highly parameterized and procedurally described in a hierarchical manner. The layout is automatically generated using a LISP-embedded procedural description language, ICPL, and is independent of design rule changes as a result of parameterization. This paper describes the DATAPATH Silicon Assembler synthesis process which includes the users' interface, the automatic layout generation, the architecture, library and the verification process, all in a single engineering workstation system.</description><subject>Applied computing -- Physical sciences and engineering -- Engineering</subject><subject>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization</subject><subject>Hardware -- Electronic design automation -- Physical design (EDA)</subject><subject>Hardware -- Robustness</subject><subject>Hardware -- Very large scale integration design</subject><isbn>0818607025</isbn><isbn>9780818607028</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1986</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNqNj0tLAzEUhQMiVGuX_QuunHrvTW4ey6E-KhR0MfuQmUmgdepoY_-_kRHc9mzO5uMcPiGWCCsuuZdoAeWqFCp3Ia7BotVggHgmFjnvAQCRgJGuxOyhbuq3utnciMsUhhwXfz0XzdNjs95U29fnl3W9rYJzXCmNsjOWyUFiS45Ymt6yAlCgdQraRoS-LCsC6lOgcswOXMTYtr0zci5up9nP4_h1ivnbH3a5i8MQPuJ4yl4iGoWW_8HQHXw7ju_ZI_hfPz_5-cmvgHdngb497mKSPwnSStU</recordid><startdate>19860702</startdate><enddate>19860702</enddate><creator>Marshburn, Tom</creator><creator>Lui, Ivy</creator><creator>Brown, Rick</creator><creator>Cheung, Dan</creator><creator>Lum, Gary</creator><creator>Cheng, Peter</creator><general>IEEE Press</general><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19860702</creationdate><title>DATAPATH</title><author>Marshburn, Tom ; Lui, Ivy ; Brown, Rick ; Cheung, Dan ; Lum, Gary ; Cheng, Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a995-4613c785290f58292537d854004066fa68e10d5124202dfa28605909e1ebbd973</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1986</creationdate><topic>Applied computing -- Physical sciences and engineering -- Engineering</topic><topic>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization</topic><topic>Hardware -- Electronic design automation -- Physical design (EDA)</topic><topic>Hardware -- Robustness</topic><topic>Hardware -- Very large scale integration design</topic><toplevel>online_resources</toplevel><creatorcontrib>Marshburn, Tom</creatorcontrib><creatorcontrib>Lui, Ivy</creatorcontrib><creatorcontrib>Brown, Rick</creatorcontrib><creatorcontrib>Cheung, Dan</creatorcontrib><creatorcontrib>Lum, Gary</creatorcontrib><creatorcontrib>Cheng, Peter</creatorcontrib><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Marshburn, Tom</au><au>Lui, Ivy</au><au>Brown, Rick</au><au>Cheung, Dan</au><au>Lum, Gary</au><au>Cheng, Peter</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>DATAPATH: a CMOS data path silicon assembler</atitle><btitle>Proceedings of the 23rd ACM/IEEE Design Automation Conference</btitle><date>1986-07-02</date><risdate>1986</risdate><spage>722</spage><epage>729</epage><pages>722-729</pages><isbn>0818607025</isbn><isbn>9780818607028</isbn><abstract>As an integration of automatic silicon assembly and simulation tools, the DATAPATH Silicon Assembler produces mask geometries and netlists from input specifications written in a Hardware Description Language, MADL. DATAPATH consists of a library of data path cells (i.e. registers, bus prechargers, drivers, interconnects, ALU's and other logic elements) in a flexible bus architecture. The cells are highly parameterized and procedurally described in a hierarchical manner. The layout is automatically generated using a LISP-embedded procedural description language, ICPL, and is independent of design rule changes as a result of parameterization. This paper describes the DATAPATH Silicon Assembler synthesis process which includes the users' interface, the automatic layout generation, the architecture, library and the verification process, all in a single engineering workstation system.</abstract><cop>Piscataway, NJ, USA</cop><pub>IEEE Press</pub><doi>10.5555/318013.318149</doi><tpages>8</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISBN: 0818607025 |
| ispartof | Proceedings of the 23rd ACM/IEEE Design Automation Conference, 1986, p.722-729 |
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| language | eng |
| recordid | cdi_acm_books_10_5555_318013_318149 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied computing -- Physical sciences and engineering -- Engineering Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization Hardware -- Electronic design automation -- Physical design (EDA) Hardware -- Robustness Hardware -- Very large scale integration design |
| title | DATAPATH: a CMOS data path silicon assembler |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T12%3A40%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_acm_b&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=DATAPATH:%20a%20CMOS%20data%20path%20silicon%20assembler&rft.btitle=Proceedings%20of%20the%2023rd%20ACM/IEEE%20Design%20Automation%20Conference&rft.au=Marshburn,%20Tom&rft.date=1986-07-02&rft.spage=722&rft.epage=729&rft.pages=722-729&rft.isbn=0818607025&rft.isbn_list=9780818607028&rft_id=info:doi/10.5555/318013.318149&rft_dat=%3Cproquest_acm_b%3E31174185%3C/proquest_acm_b%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=31174185&rft_id=info:pmid/&rfr_iscdi=true |