HERCULES-a system for high-level synthesis
This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation...
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creator | De Micheli, Giovanni Ku, David C. |
description | This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor. |
doi_str_mv | 10.5555/285730.285808 |
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fullrecord | <record><control><sourceid>acm</sourceid><recordid>TN_cdi_acm_books_10_5555_285730_285808_brief</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>acm_books_10_5555_285730_285808</sourcerecordid><originalsourceid>FETCH-LOGICAL-a136t-14ef9e66152f5b5509761617279a4379e400314c214a3d7ecdc04c370709b7143</originalsourceid><addsrcrecordid>eNqNj01Lw0AURQdEUNsu3WflQkx9L_PxZpYSYisECmrXw2Q6Y6KpgU4Q_PdG4g_wbi5cDhcOY9cIaznlvtCSOKyn0qDP2BVo1EprJeQFW6X0DlOIjJTFJbvdVs_lvq5ecpel7zSGYxaHU9Z2b23eh6_QT-vn2IbUpSU7j65PYfXXC7Z_rF7LbV7vNk_lQ5075GrMUYRoglIoiygbKcGQQoVUkHGCkwkCgKPwBQrHDxT8wYPwnIDANISCL9jd_Ov80TbD8JEsgv01s7OZnc1sc-pCnPCbf-H8B2pMS2g</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>HERCULES-a system for high-level synthesis</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>De Micheli, Giovanni ; Ku, David C.</creator><creatorcontrib>De Micheli, Giovanni ; Ku, David C.</creatorcontrib><description>This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor.</description><identifier>ISBN: 0818688645</identifier><identifier>ISBN: 9780818688645</identifier><identifier>DOI: 10.5555/285730.285808</identifier><language>eng</language><publisher>Los Alamitos, CA, USA: IEEE Computer Society Press</publisher><subject>Applied computing -- Physical sciences and engineering -- Engineering ; Hardware -- Electronic design automation -- High-level and register-transfer level synthesis ; Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization ; Hardware -- Electronic design automation -- Physical design (EDA) ; Hardware -- Very large scale integration design</subject><ispartof>Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, p.483-488</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>309,310,776,780,785,786,27902</link.rule.ids></links><search><creatorcontrib>De Micheli, Giovanni</creatorcontrib><creatorcontrib>Ku, David C.</creatorcontrib><title>HERCULES-a system for high-level synthesis</title><title>Proceedings of the 25th ACM/IEEE Design Automation Conference</title><description>This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor.</description><subject>Applied computing -- Physical sciences and engineering -- Engineering</subject><subject>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis</subject><subject>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization</subject><subject>Hardware -- Electronic design automation -- Physical design (EDA)</subject><subject>Hardware -- Very large scale integration design</subject><isbn>0818688645</isbn><isbn>9780818688645</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1988</creationdate><recordtype>conference_proceeding</recordtype><sourceid/><recordid>eNqNj01Lw0AURQdEUNsu3WflQkx9L_PxZpYSYisECmrXw2Q6Y6KpgU4Q_PdG4g_wbi5cDhcOY9cIaznlvtCSOKyn0qDP2BVo1EprJeQFW6X0DlOIjJTFJbvdVs_lvq5ecpel7zSGYxaHU9Z2b23eh6_QT-vn2IbUpSU7j65PYfXXC7Z_rF7LbV7vNk_lQ5075GrMUYRoglIoiygbKcGQQoVUkHGCkwkCgKPwBQrHDxT8wYPwnIDANISCL9jd_Ov80TbD8JEsgv01s7OZnc1sc-pCnPCbf-H8B2pMS2g</recordid><startdate>19880601</startdate><enddate>19880601</enddate><creator>De Micheli, Giovanni</creator><creator>Ku, David C.</creator><general>IEEE Computer Society Press</general><scope/></search><sort><creationdate>19880601</creationdate><title>HERCULES-a system for high-level synthesis</title><author>De Micheli, Giovanni ; Ku, David C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a136t-14ef9e66152f5b5509761617279a4379e400314c214a3d7ecdc04c370709b7143</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Applied computing -- Physical sciences and engineering -- Engineering</topic><topic>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis</topic><topic>Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization</topic><topic>Hardware -- Electronic design automation -- Physical design (EDA)</topic><topic>Hardware -- Very large scale integration design</topic><toplevel>online_resources</toplevel><creatorcontrib>De Micheli, Giovanni</creatorcontrib><creatorcontrib>Ku, David C.</creatorcontrib></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>De Micheli, Giovanni</au><au>Ku, David C.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>HERCULES-a system for high-level synthesis</atitle><btitle>Proceedings of the 25th ACM/IEEE Design Automation Conference</btitle><date>1988-06-01</date><risdate>1988</risdate><spage>483</spage><epage>488</epage><pages>483-488</pages><isbn>0818688645</isbn><isbn>9780818688645</isbn><abstract>This paper presents an approach to high-level synthesis of VLSI processors and systems. Synthesis consists of two phases: behavioral synthesis, which involves implementation-independent representations, and structural synthesis, that relates to the transformation of a behavior into an implementation. We describe HERCULES, a system for high-level synthesis developed at Stanford University. In particular, we address the hardware description problem, behavioral synthesis and optimization using a method called the reference stack, and the mapping of behavior onto a structure. We present a model for control based on sequencing graphs that supports multiple threads of execution flow, allowing varying degree of parallelism in the resulting hardware. Results are then presented for three examples: MC6502, Intel8251 and FRISC, a 16-bit microprocessor.</abstract><cop>Los Alamitos, CA, USA</cop><pub>IEEE Computer Society Press</pub><doi>10.5555/285730.285808</doi><tpages>6</tpages></addata></record> |
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identifier | ISBN: 0818688645 |
ispartof | Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, p.483-488 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Applied computing -- Physical sciences and engineering -- Engineering Hardware -- Electronic design automation -- High-level and register-transfer level synthesis Hardware -- Electronic design automation -- High-level and register-transfer level synthesis -- Datapath optimization Hardware -- Electronic design automation -- Physical design (EDA) Hardware -- Very large scale integration design |
title | HERCULES-a system for high-level synthesis |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T04%3A32%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-acm&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=HERCULES-a%20system%20for%20high-level%20synthesis&rft.btitle=Proceedings%20of%20the%2025th%20ACM/IEEE%20Design%20Automation%20Conference&rft.au=De%20Micheli,%20Giovanni&rft.date=1988-06-01&rft.spage=483&rft.epage=488&rft.pages=483-488&rft.isbn=0818688645&rft.isbn_list=9780818688645&rft_id=info:doi/10.5555/285730.285808&rft_dat=%3Cacm%3Eacm_books_10_5555_285730_285808%3C/acm%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |