Temporal verification of behavioral descriptions in VHDL

This paper presents an approach for verifying the temporal scheduling of behavioral models of VHDL. The aim is to verify that the control flow of a behavioral description satisfies its behavioral specifications described in a formalism based on verified temporal logics and on a notion of physical ac...

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Bibliographische Detailangaben
Hauptverfasser:	Boussebha, Djamel, Giambiasi, Norbert, Magnier, Janine
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Hardware > Hardware validation > Functional verification Hardware > Integrated circuits > Logic circuits Hardware > Very large scale integration design Theory of computation > Logic Theory of computation > Models of computation > Computability
Online-Zugang:	Volltext
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