Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware

Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller Logic (PMRML) to overcome the glitch and Dissipation Timing Skew (DTS) problems in design of DPA-resistant cryptographic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Lin, Kuan Jen, Fan, Shan Chien, Yang, Shih Hsien, Lo, Cheng Chia
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Hardware Hardware > Hardware validation
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!