Automatic abstraction and verification of verilog models
Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of th...
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| creator | Andraus, Zaher S. Sakallah, Karem A. |
| description | Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification. |
| doi_str_mv | 10.1145/996566.996629 |
| format | Conference Proceeding |
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A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. 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A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification.</description><subject>Abstracts</subject><subject>Applied sciences</subject><subject>Arithmetic</subject><subject>Computer bugs</subject><subject>Counting circuits</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Formal verification</subject><subject>Hardware -- Hardware validation -- Functional verification</subject><subject>Hardware design languages</subject><subject>Integrated circuits</subject><subject>Logic</subject><subject>Permission</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Size control</subject><subject>State-space methods</subject><issn>0738-100X</issn><isbn>1581138288</isbn><isbn>9781581138283</isbn><isbn>1511838288</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2004</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDtLA0EURgdUMMaUVjbbaOXGee08yhB8QcBGwW6485LR3UzYWQX_vWtWsPU2H_d-h1schM4IXhLCm2utRSPEcgxB9QE6IY0ihCmq1CGaYclUTTB-OUaLUt7wOFJqydkMqdXHkDsYkqvAlqEHN6S8rWDrq8_Qp5gc7A857vc2v1Zd9qEtp-goQlvC4jfn6Pn25ml9X28e7x7Wq00NTIqhVmBjEI4CJ9ph7wn2xFkuMFXYBhatxURTCL4R1GPpOA-NjFEIpSKApmyOLqa_OygO2tjD1qVidn3qoP8yRDLecMFH7nziUgjhr2aUcvnTXk4tuM7YnN-LIdj8mDOTOTOZG8Grf4HG9ilE9g3CAWud</recordid><startdate>20040101</startdate><enddate>20040101</enddate><creator>Andraus, Zaher S.</creator><creator>Sakallah, Karem A.</creator><general>ACM</general><general>IEEE</general><general>Association for Computing Machinery</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>IQODW</scope></search><sort><creationdate>20040101</creationdate><title>Automatic abstraction and verification of verilog models</title><author>Andraus, Zaher S. ; Sakallah, Karem A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a376t-8abfe6c2a419c0dd10d1cb460280be3fbb0192aed562d07c44e57ff6688faa923</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Abstracts</topic><topic>Applied sciences</topic><topic>Arithmetic</topic><topic>Computer bugs</topic><topic>Counting circuits</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Formal verification</topic><topic>Hardware -- Hardware validation -- Functional verification</topic><topic>Hardware design languages</topic><topic>Integrated circuits</topic><topic>Logic</topic><topic>Permission</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Size control</topic><topic>State-space methods</topic><toplevel>online_resources</toplevel><creatorcontrib>Andraus, Zaher S.</creatorcontrib><creatorcontrib>Sakallah, Karem A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Andraus, Zaher S.</au><au>Sakallah, Karem A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Automatic abstraction and verification of verilog models</atitle><btitle>Proceedings of the 41st annual Design Automation Conference</btitle><stitle>DAC</stitle><date>2004-01-01</date><risdate>2004</risdate><spage>218</spage><epage>223</epage><pages>218-223</pages><issn>0738-100X</issn><isbn>1581138288</isbn><isbn>9781581138283</isbn><isbn>1511838288</isbn><abstract>Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. 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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0738-100X |
| ispartof | Proceedings of the 41st annual Design Automation Conference, 2004, p.218-223 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_acm_books_10_1145_996566_996629 |
| source | IEEE Electronic Library (IEL) |
| subjects | Abstracts Applied sciences Arithmetic Computer bugs Counting circuits Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Formal verification Hardware -- Hardware validation -- Functional verification Hardware design languages Integrated circuits Logic Permission Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Size control State-space methods |
| title | Automatic abstraction and verification of verilog models |
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