Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large...

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Bibliographische Detailangaben
Hauptverfasser:	Kajihara, Seiji, Pomeranz, Irith, Kinoshita, Kozo, Reddy, Sudhakar M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit faults Circuit testing Cities and towns Combinational circuits Electrical fault detection Fault detection Flip-flops Hardware > Hardware test > Test-pattern generation and fault simulation Hardware > Integrated circuits > Logic circuits > Combinational circuits Logic testing Physics computing Test pattern generators
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