Full-system chip multiprocessor power evaluations using FPGA-based emulation
The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including appl...
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creator | Bhattacharjee, Abhishek Contreras, Gilberto Martonosi, Margaret |
description | The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems. |
doi_str_mv | 10.1145/1393921.1394010 |
format | Conference Proceeding |
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In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. 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In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.</description><subject>activity migration</subject><subject>Application software</subject><subject>Computer systems organization -- Architectures -- Parallel architectures</subject><subject>Counting circuits</subject><subject>Emulation</subject><subject>Feeds</subject><subject>full-system fpga-based emulation</subject><subject>General and reference -- Cross-computing tools and techniques -- Measurement</subject><subject>General and reference -- Cross-computing tools and techniques -- Metrics</subject><subject>Hardware -- Hardware validation</subject><subject>Linux</subject><subject>Microarchitecture</subject><subject>Operating systems</subject><subject>power models</subject><subject>Power system modeling</subject><subject>Process design</subject><subject>Temperature</subject><isbn>9781605581095</isbn><isbn>1605581097</isbn><isbn>9781424486342</isbn><isbn>1424486343</isbn><isbn>9781605581095</isbn><isbn>1605581097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDFPwzAQRo0QEqh0ZmDxyJJy58RJPFYVLUiVYIDZsp0zGJImihNQ_z2BdmJi-nR6ejc8xq4QFoiZvMVUpUrgYtoMEE7YXBUl5iBliaDk6Z_7nM1jfAcAnAQsywu2XY91ncR9HKjh7i10vBnrIXR96yjGtudd-0U9p09Tj2YI7S7yMYbdK18_bZaJNZEqTpPyyy7ZmTd1pPlxZ-xlffe8uk-2j5uH1XKbGMzFkFSVdFZ5QUIQqhKKwngq0DinPNjKlp4sQpbn0qTWVlkuMgJlczC-AutsOmPXh7-BiHTXh8b0ey2lUCDkRBcHalyjbdt-RI2gf3LpYy59zKVtH8hPws0_hfQbO4JpWw</recordid><startdate>20080811</startdate><enddate>20080811</enddate><creator>Bhattacharjee, Abhishek</creator><creator>Contreras, Gilberto</creator><creator>Martonosi, Margaret</creator><general>ACM</general><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20080811</creationdate><title>Full-system chip multiprocessor power evaluations using FPGA-based emulation</title><author>Bhattacharjee, Abhishek ; Contreras, Gilberto ; Martonosi, Margaret</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a162t-dd5cb9f2e22e198077afe71acc9f0bdb8feb104665a3bbd4624e09b60afd0bcb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>activity migration</topic><topic>Application software</topic><topic>Computer systems organization -- Architectures -- Parallel architectures</topic><topic>Counting circuits</topic><topic>Emulation</topic><topic>Feeds</topic><topic>full-system fpga-based emulation</topic><topic>General and reference -- Cross-computing tools and techniques -- Measurement</topic><topic>General and reference -- Cross-computing tools and techniques -- Metrics</topic><topic>Hardware -- Hardware validation</topic><topic>Linux</topic><topic>Microarchitecture</topic><topic>Operating systems</topic><topic>power models</topic><topic>Power system modeling</topic><topic>Process design</topic><topic>Temperature</topic><toplevel>online_resources</toplevel><creatorcontrib>Bhattacharjee, Abhishek</creatorcontrib><creatorcontrib>Contreras, Gilberto</creatorcontrib><creatorcontrib>Martonosi, Margaret</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bhattacharjee, Abhishek</au><au>Contreras, Gilberto</au><au>Martonosi, Margaret</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Full-system chip multiprocessor power evaluations using FPGA-based emulation</atitle><btitle>Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)</btitle><stitle>LPE</stitle><date>2008-08-11</date><risdate>2008</risdate><spage>335</spage><epage>340</epage><pages>335-340</pages><isbn>9781605581095</isbn><isbn>1605581097</isbn><isbn>9781424486342</isbn><isbn>1424486343</isbn><eisbn>9781605581095</eisbn><eisbn>1605581097</eisbn><abstract>The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/1393921.1394010</doi><tpages>6</tpages></addata></record> |
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ispartof | Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), 2008, p.335-340 |
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language | eng |
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subjects | activity migration Application software Computer systems organization -- Architectures -- Parallel architectures Counting circuits Emulation Feeds full-system fpga-based emulation General and reference -- Cross-computing tools and techniques -- Measurement General and reference -- Cross-computing tools and techniques -- Metrics Hardware -- Hardware validation Linux Microarchitecture Operating systems power models Power system modeling Process design Temperature |
title | Full-system chip multiprocessor power evaluations using FPGA-based emulation |
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