A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to fault-tolerant, Massively Parallel Multi-Processors Systems on Chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topolog...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Zhang, Zhen, Greiner, Alain, Taktak, Sami
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	2D-Mesh NoC Algorithm design and analysis Computer Science Computer systems organization > Architectures > Parallel architectures > Interconnection architectures Costs DSPIN Fault detection Fault tolerance fault-tolerant Hardware Hardware > Hardware test Hardware > Robustness Hardware Architecture MP2-SoC Network topology Network-on-a-chip reconfiguration Routing routing algorithm Silicon System-on-a-chip
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!