Placement of 3D ICs with thermal and interlayer via considerations

Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between...

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Bibliographische Detailangaben
Hauptverfasser:	Goplen, Brent, Spatnekar, Sachin
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3-D IC 3-D VLSI Algorithm design and analysis Algorithms Computational modeling Design Experimentation Hardware > Electronic design automation > Physical design (EDA) > Placement Hardware > Electronic design automation > Physical design (EDA) > Wire routing Hardware > Emerging technologies Heat sinks Integrated circuit technology interlayer vias placement Power dissipation Power distribution Routing temperature Temperature distribution Thermal conductivity thermal optimization Three-dimensional integrated circuits
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