Placement of 3D ICs with thermal and interlayer via considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between...
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| creator | Goplen, Brent Spatnekar, Sachin |
| description | Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias. |
| doi_str_mv | 10.1145/1278480.1278637 |
| format | Conference Proceeding |
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Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 1595936270</identifier><identifier>ISBN: 9781595936271</identifier><identifier>DOI: 10.1145/1278480.1278637</identifier><language>eng</language><publisher>New York, NY, USA: ACM</publisher><subject>3-D IC ; 3-D VLSI ; Algorithm design and analysis ; Algorithms ; Computational modeling ; Design ; Experimentation ; Hardware -- Electronic design automation -- Physical design (EDA) -- Placement ; Hardware -- Electronic design automation -- Physical design (EDA) -- Wire routing ; Hardware -- Emerging technologies ; Heat sinks ; Integrated circuit technology ; interlayer vias ; placement ; Power dissipation ; Power distribution ; Routing ; temperature ; Temperature distribution ; Thermal conductivity ; thermal optimization ; Three-dimensional integrated circuits</subject><ispartof>2007 44th ACM/IEEE Design Automation Conference, 2007, p.626-631</ispartof><rights>2007 ACM</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-a1692-b380bcc3feda309e98f0eb755b2fa528c22cdaf5f40a8e72d41f3bee3ceaf10e3</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4261258$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,792,2051,27904,54737,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4261258$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Goplen, Brent</creatorcontrib><creatorcontrib>Spatnekar, Sachin</creatorcontrib><title>Placement of 3D ICs with thermal and interlayer via considerations</title><title>2007 44th ACM/IEEE Design Automation Conference</title><addtitle>DAC</addtitle><description>Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.</description><subject>3-D IC</subject><subject>3-D VLSI</subject><subject>Algorithm design and analysis</subject><subject>Algorithms</subject><subject>Computational modeling</subject><subject>Design</subject><subject>Experimentation</subject><subject>Hardware -- Electronic design automation -- Physical design (EDA) -- Placement</subject><subject>Hardware -- Electronic design automation -- Physical design (EDA) -- Wire routing</subject><subject>Hardware -- Emerging technologies</subject><subject>Heat sinks</subject><subject>Integrated circuit technology</subject><subject>interlayer vias</subject><subject>placement</subject><subject>Power dissipation</subject><subject>Power distribution</subject><subject>Routing</subject><subject>temperature</subject><subject>Temperature distribution</subject><subject>Thermal conductivity</subject><subject>thermal optimization</subject><subject>Three-dimensional integrated circuits</subject><issn>0738-100X</issn><isbn>1595936270</isbn><isbn>9781595936271</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDtPwzAUhS0BEqV0ZmDxhFhS_EycEcqrUiUYQGKzbpxr1ZAH2Cmo_56g9gcwnXN1Pt3hI-SMsznnSl9xURhlxmPMXBYH5ITrUpcyFwU7JBNWSJNxxt6OySyld8YY59IIVUzIzXMDDlvsBtp7Km_pcpHoTxjWdFhjbKGh0NU0dAPGBrYY6XcA6vouhRojDGFsp-TIQ5Nwts8peb2_e1k8Zqunh-XiepUBz0uRVdKwyjnpsQbJSiyNZ1gVWlfCgxbGCeFq8NorBgYLUSvuZYUoHYLnDOWUXOz-fsb-a4NpsG1IDpsGOuw3yUquRKlKMYLnOzAgov2MoYW4tUrkXGgzrpe7FVxrq77_SJYz-6fR7jXavcYRnf8TtVUM6OUv5_1wlw</recordid><startdate>20070604</startdate><enddate>20070604</enddate><creator>Goplen, Brent</creator><creator>Spatnekar, Sachin</creator><general>ACM</general><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20070604</creationdate><title>Placement of 3D ICs with thermal and interlayer via considerations</title><author>Goplen, Brent ; Spatnekar, Sachin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a1692-b380bcc3feda309e98f0eb755b2fa528c22cdaf5f40a8e72d41f3bee3ceaf10e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>3-D IC</topic><topic>3-D VLSI</topic><topic>Algorithm design and analysis</topic><topic>Algorithms</topic><topic>Computational modeling</topic><topic>Design</topic><topic>Experimentation</topic><topic>Hardware -- Electronic design automation -- Physical design (EDA) -- Placement</topic><topic>Hardware -- Electronic design automation -- Physical design (EDA) -- Wire routing</topic><topic>Hardware -- Emerging technologies</topic><topic>Heat sinks</topic><topic>Integrated circuit technology</topic><topic>interlayer vias</topic><topic>placement</topic><topic>Power dissipation</topic><topic>Power distribution</topic><topic>Routing</topic><topic>temperature</topic><topic>Temperature distribution</topic><topic>Thermal conductivity</topic><topic>thermal optimization</topic><topic>Three-dimensional integrated circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Goplen, Brent</creatorcontrib><creatorcontrib>Spatnekar, Sachin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Goplen, Brent</au><au>Spatnekar, Sachin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Placement of 3D ICs with thermal and interlayer via considerations</atitle><btitle>2007 44th ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>2007-06-04</date><risdate>2007</risdate><spage>626</spage><epage>631</epage><pages>626-631</pages><issn>0738-100X</issn><isbn>1595936270</isbn><isbn>9781595936271</isbn><abstract>Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/1278480.1278637</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0738-100X |
| ispartof | 2007 44th ACM/IEEE Design Automation Conference, 2007, p.626-631 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_acm_books_10_1145_1278480_1278637 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | 3-D IC 3-D VLSI Algorithm design and analysis Algorithms Computational modeling Design Experimentation Hardware -- Electronic design automation -- Physical design (EDA) -- Placement Hardware -- Electronic design automation -- Physical design (EDA) -- Wire routing Hardware -- Emerging technologies Heat sinks Integrated circuit technology interlayer vias placement Power dissipation Power distribution Routing temperature Temperature distribution Thermal conductivity thermal optimization Three-dimensional integrated circuits |
| title | Placement of 3D ICs with thermal and interlayer via considerations |
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