Chip multi-processor generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform that will supersede the microprocessor. We argue that these flexible, general computing chip...
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creator | Solomatnikov, Alex Firoozshahian, Amin Qadeer, Wajahat Shacham, Ofer Kelley, Kyle Asgar, Zain Wachs, Megan Hameed, Rehan Horowitz, Mark |
description | The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform that will supersede the microprocessor. We argue that these flexible, general computing chips are trying to accomplish more than is commercially needed. Since design NRE costs are an order of magnitude larger than fabrication NRE costs, a two-step design system seems attractive. First, the users configure/program a flexible computing framework to run their application with the desired performance. Then, the system "compiles" the program and configuration, tailoring the original framework to create a chip that is optimized toward the desired set of applications. Thus the user gets the reduced development costs of using a flexible solution with the efficiency of a custom chip. |
doi_str_mv | 10.1145/1278480.1278544 |
format | Conference Proceeding |
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identifier | ISSN: 0738-100X |
ispartof | 2007 44th ACM/IEEE Design Automation Conference, 2007, p.262-263 |
issn | 0738-100X |
language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Algorithm design and analysis Algorithms Application specific integrated circuits Chip Multi-Processor CMOS technology Cost function Design Design optimization Fabrication Hardware Hardware -- Electronic design automation -- Physical design (EDA) High performance computing High-Level Design Microprocessors Permission |
title | Chip multi-processor generator |
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