Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Th...
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creator | Hua, Hao Mineo, Chris Schoenfliess, Kory Sule, Ambarish Melamed, Samson Jenkal, Ravi Davis, W. Rhett |
description | Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system. |
doi_str_mv | 10.1145/1146909.1147161 |
format | Conference Proceeding |
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Rhett</creator><creatorcontrib>Hua, Hao ; Mineo, Chris ; Schoenfliess, Kory ; Sule, Ambarish ; Melamed, Samson ; Jenkal, Ravi ; Davis, W. Rhett</creatorcontrib><description>Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. 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Rhett</creatorcontrib><title>Exploring compromises among timing, power and temperature in three-dimensional integrated circuits</title><title>2006 43rd ACM/IEEE Design Automation Conference</title><addtitle>DAC</addtitle><description>Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system.</description><subject>3DIC</subject><subject>Delay effects</subject><subject>Design</subject><subject>design flow</subject><subject>Digital systems</subject><subject>Experimentation</subject><subject>Hardware</subject><subject>Hardware -- Hardware validation</subject><subject>Hardware -- Very large scale integration design</subject><subject>Integrated circuit interconnections</subject><subject>Power system interconnection</subject><subject>Routing</subject><subject>Stacking</subject><subject>Temperature</subject><subject>temperature dependency</subject><subject>Thermal conductivity</subject><subject>Three-dimensional integrated circuits</subject><subject>Timing</subject><subject>trade off</subject><issn>0738-100X</issn><isbn>1595933816</isbn><isbn>9781595933812</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkD9PwzAQxS0BEqV0ZmDJhBhI8cVObI-oKn-kSiwgsVmOcy2GJA52KuDb46r9ACx3uvd-Ouk9Qi6AzgF4eZtGpajaHQIqOCJnUKpSMSahOiYTKpjMgdK3UzKL8YNSCsBkwcsJqZc_Q-uD6zeZ9d0QfOcixsx0Pimj65Jxkw3-G0Nm-iYbsRswmHEbMHN9Nr4HxLxxHfbR-d60SRxxkwBsMuuC3boxnpOTtWkjzg57Sl7vly-Lx3z1_PC0uFvlpijVmGMt0QLUtKhYWRhVUK7WSklAwZlQAhVbg60FbzgtwAoQltYAiFzWzAjBpuRq_zel-NpiHHXKYrFtTY9-GzUDQQtJd-DlHnSIqIfgOhN-NVRSKs6Te713je107f1n1ED1rmZ9qFkfak7o_J-oroPDNfsDQCt78g</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Hua, Hao</creator><creator>Mineo, Chris</creator><creator>Schoenfliess, Kory</creator><creator>Sule, Ambarish</creator><creator>Melamed, Samson</creator><creator>Jenkal, Ravi</creator><creator>Davis, W. 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Rhett</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a259t-eb8ec11b026352a92049f9981e743797e93f1cb74d4021c717c0b11ee48b3a773</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>3DIC</topic><topic>Delay effects</topic><topic>Design</topic><topic>design flow</topic><topic>Digital systems</topic><topic>Experimentation</topic><topic>Hardware</topic><topic>Hardware -- Hardware validation</topic><topic>Hardware -- Very large scale integration design</topic><topic>Integrated circuit interconnections</topic><topic>Power system interconnection</topic><topic>Routing</topic><topic>Stacking</topic><topic>Temperature</topic><topic>temperature dependency</topic><topic>Thermal conductivity</topic><topic>Three-dimensional integrated circuits</topic><topic>Timing</topic><topic>trade off</topic><toplevel>online_resources</toplevel><creatorcontrib>Hua, Hao</creatorcontrib><creatorcontrib>Mineo, Chris</creatorcontrib><creatorcontrib>Schoenfliess, Kory</creatorcontrib><creatorcontrib>Sule, Ambarish</creatorcontrib><creatorcontrib>Melamed, Samson</creatorcontrib><creatorcontrib>Jenkal, Ravi</creatorcontrib><creatorcontrib>Davis, W. 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Rhett</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Exploring compromises among timing, power and temperature in three-dimensional integrated circuits</atitle><btitle>2006 43rd ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>2006</date><risdate>2006</risdate><spage>997</spage><epage>1002</epage><pages>997-1002</pages><issn>0738-100X</issn><isbn>1595933816</isbn><isbn>9781595933812</isbn><abstract>Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/1146909.1147161</doi><tpages>6</tpages></addata></record> |
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identifier | ISSN: 0738-100X |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | 3DIC Delay effects Design design flow Digital systems Experimentation Hardware Hardware -- Hardware validation Hardware -- Very large scale integration design Integrated circuit interconnections Power system interconnection Routing Stacking Temperature temperature dependency Thermal conductivity Three-dimensional integrated circuits Timing trade off |
title | Exploring compromises among timing, power and temperature in three-dimensional integrated circuits |
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