The V-Way Cache: Demand Based Associativity via Global Replacement

As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of current set-associative caches is reduced because programs exhibit a non-uniform distribution of memory accesses across diffe...

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Hauptverfasser: Qureshi, Moinuddin K., Thompson, David, Patt, Yale N.
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description As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of current set-associative caches is reduced because programs exhibit a non-uniform distribution of memory accesses across different cache sets. We propose a technique to vary the associativity of a cache on a per-set basis in response to the demands of the program. By increasing the number of tag-store entries relative to the number of data lines, we achieve the performance benefit of global replacement while maintaining the constant hit latency of a set-associative cache. The proposed variable-way, or V-Way, set-associative cache achieves an average miss rate reduction of 13% on sixteen benchmarks from the SPEC CPU2000 suite. This translates into an average IPC improvement of 8%.
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identifier ISSN: 1063-6897
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer systems organization -- Architectures -- Parallel architectures
Costs
Delay
Energy consumption
Engineering management
Hardware
Hardware -- Electronic design automation -- High-level and register-transfer level synthesis
Hardware -- Electronic design automation -- Modeling and parameter extraction
Hardware -- Integrated circuits
Hardware -- Integrated circuits -- Semiconductor memory
History
Memory management
Microprocessors
Optimized production technology
Upper bound
title The V-Way Cache: Demand Based Associativity via Global Replacement
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