SNaP: A novel hybrid method for circuit reliability assessment under multiple faults von Pagliarini, S.N., Ben Dhia, A., Naviner, L.A. de B., Naviner, J.-F.

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Exploring the feasibility of selective hardening for combinational logic von Pagliarini, S.N., dos Santos, G.G., de B. Naviner, L.A., Naviner, J.-F.

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Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method von An, T., Liu, K., Cai, H., de B. Naviner, L.A.

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A dual-rail compact defect-tolerant multiplexer von Ben Dhia, A., Slimani, M., Cai, H., de B. Naviner, L.A.

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A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs von Ben Dhia, A., Pagliarini, S.N., de B. Naviner, L.A., Mehrez, H., Matherat, P.

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Using error tolerance of target application for efficient reliability improvement of digital circuits von dos Santos, G.G., Marques, E.C., Naviner, L.A. de B., Naviner, J.-F.

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Hardware implementation issues of a BMS decoding approach for AG based codes von Belkoura, Z., de B Naviner, L.A.

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Reliability analysis of combinational circuits based on a probabilistic binomial model von de Vasconcelos, M., Franco, D.T., de B. Naviner, L.A., Naviner, J.-F.

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On the output events in concurrent error detection schemes von de Vasconcelos, M.C.R., Franco, D.T., de B. Naviner, L.A., Naviner, J.-F.

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