Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs von Nosrati, Nooshin, Navabi, Zainalabedin

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An Efficient RTL Design for a Wearable Brain–Computer Interface von Vasei, Tahereh, Saber, Mohammad Ali, Nahvy, Alireza, Navabi, Zainalabedin

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Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators von Nahvy, Alireza, Navabi, Zainalabedin

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Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information von Ebrahimi, Mohammad, Navabi, Zainalabedin

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Self-Healing Many-Core Architecture: Analysis and Evaluation von Kamran, Arezoo, Navabi, Zainalabedin

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LUT Input Reordering to Reduce Aging Impact on FPGA LUTs von Ebrahimi, Mohammad, Sadeghi, Rezgar, Navabi, Zainalabedin

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BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs von Lotfi-Kamran, P., Daneshtalab, M., Lucas, C., Navabi, Z.

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SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs von Ghaderi, Zana, Ebrahimi, Mohammad, Navabi, Zainalabedin, Bozorgzadeh, Eli, Bagherzadeh, Nader

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Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors von Refan, Fatemeh, Alizadeh, Bijan, Navabi, Zainalabedin

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Stochastic testing of processing cores in a many-core architecture von Kamran, Arezoo, Navabi, Zainalabedin

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Automatic Correction of Dynamic Power Management Architecture in Modern Processors von Sharafinejad, Reza, Alizadeh, Bijan, Navabi, Zainalabedin

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Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors von Refan, Fatemeh, Alizadeh, Bijan, Navabi, Zainalabedin

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Self-Adjusting Monitor for Measuring Aging Rate and Advancement von Sadeghi-Kohan, Somayeh, Kamal, Mehdi, Navabi, Zainalabedin

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System-level assertions: approach for electronic system-level verification von Sohofi, Hassan, Navabi, Zainalabedin

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Hardware Acceleration of Online Error Detection in Many-Core Processors von Kamran, Arezoo, Navabi, Zainalabedin

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Test access to deeply embedded analog terminals within an A/MS SoC von Niaraki, Asli Rahebeh, Mirzakuchaki, Sattar, Navabi, Zainalabedin, Renovell, Michel

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A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies von Ansari, Mohammad, Afzali-Kusha, Hassan, Ebrahimi, Behzad, Navabi, Zainalabedin, Afzali-Kusha, Ali, Pedram, Massoud

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A low-power high-throughput link splitting router for NoCs von Saneei, Mohsen, Afzali-Kusha, Ali, Navabi, Zainalabedin

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Hardware Acceleration of Online Error Detection in Many-Core Processors/L'accélération matérielle de la détection d'erreurs en ligne dans les processeurs Multi-Coeurs von Kamran, Arezoo, Navabi, Zainalabedin

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Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition von Ghandali, Samaneh, Alizadeh, Bijan, Fujita, Masahiro, Navabi, Zainalabedin

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