On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors von Shuai Wang, Jie Hu, Ziavras, S.G.

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Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks von Contreras, William, Ziavras, Sotirios

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On the Exploitation of Narrow-Width Values for Improving Register File Reliability von Jie Hu, Shuai Wang, Ziavras, S.G.

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Wireless sensor network-based pattern matching technique for the circumvention of environmental and stimuli-related variability in structural health monitoring von Contreras, William, Ziavras, Sotirios

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Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays von Shuai Wang, Jie Hu, Ziavras, S. G.

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Performance-Energy Optimizations for Shared Vector Accelerators in Multicores von Beldianu, Spiridon F., Ziavras, Sotirios G.

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Vector Coprocessor Virtualization for Simultaneous Multithreading von Lu, Yaojie, Rooholamin, Seyedamin, Ziavras, Sotirios G.

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Instruction Fusion for Multiscalar and Many-Core Processors von Lu, Yaojie, Ziavras, Sotirios G.

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A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines von Salehin, Khondaker M., Rojas-Cessa, Roberto, Ziavras, Sotirios G.

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Multicore-based vector coprocessor sharing for performance and energy gains von Beldianu, Spiridon F., Ziavras, Sotirios G.

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Self-Adaptive Data Caches for Soft-Error Reliability von Shuai Wang, Jie Hu, Ziavras, S.G.

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Online Anonymity Protection in Computer-Mediated Communication von Motahari, S, Ziavras, S G, Jones, Q

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Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm von Sajid, Imtiaz, Ahmed, M. M., Ziavras, Sotirios G.

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Scheduling for input-queued packet switches by a re-configurable parallel match evaluator von Beldianu, S.F., Rojas-Cessa, R., Oki, E., Ziavras, S.G.

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A super-programming approach for mining association rules in parallel on PC clusters von Jin, D., Ziavras, S.G.

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Efficient hardware support for pattern matching in network intrusion detection von Guinde, Nitesh B., Ziavras, Sotirios G.

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Modular vector processor architecture targeting at data-level parallelism von Rooholamin, Seyed A., Ziavras, Sotirios G.

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Parallel solution of Newton’s power flow equations on configurable chips von Wang, Xiaofang, Ziavras, Sotirios G., Nwankpa, Chika, Johnson, Jeremy, Nagvajara, Prawat

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Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines von Wang, Xiaofang, Ziavras, Sotirios G.

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RH: a versatile family of reduced hypercube interconnection networks von Ziavras, S.G.

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