Treffer 1 - 14 von 14 für Suche 'ZIAJA THOMAS ALAN', Suchdauer: 0,58s Treffer weiter einschränken
  1. 1
    A PROCESSOR UNIT WITH COMBINED MEMORY, LOGIC, AND BIST

    A PROCESSOR UNIT WITH COMBINED MEMORY, LOGIC, AND BIST von AMIRTHARAJ, Dinesh Rajasavari, ZIAJA, Thomas Alan

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  2. 2
    Built-in self-test for processor unit with combined memory and logic

    Built-in self-test for processor unit with combined memory and logic von Ziaja, Thomas Alan, Amirtharaj, Dinesh Rajasavari

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  3. 3
    Array of processor units with local BIST

    Array of processor units with local BIST von Ziaja, Thomas Alan, Amirtharaj, Dinesh Rajasavari

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  4. 4
    METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY

    METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY von AMIRTHARAJ, Dinesh Rajasavari, ZIAJA, Thomas Alan, DURAIRAJAN, Uma

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  5. 5
    Integrated circuit with embedded test functionality

    Integrated circuit with embedded test functionality von ZIAJA THOMAS ALAN, DONAHUE HUNTER S, WATKINS DANIEL R

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  6. 6
    Integrated circuit with blocking pin to coordinate entry into test mode

    Integrated circuit with blocking pin to coordinate entry into test mode von Ziaja, Thomas Alan, Woodling, Kevin D, Molyneaux, Robert F

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  7. 7
    Integrated circuit with blocking pin to coordinate entry into test mode

    Integrated circuit with blocking pin to coordinate entry into test mode von WOODLING KEVIN D, ZIAJA THOMAS ALAN, MOLYNEAUX ROBERT F

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  8. 8
    Integrated circuit with embedded test functionality

    Integrated circuit with embedded test functionality von Watkins, Daniel R, Donahue, Hunter S, Ziaja, Thomas Alan

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  9. 9
    Testing multi-core processors

    Testing multi-core processors von ZIAJA THOMAS ALAN, CATY OLIVIER FRANCIS CYRILLE, GALA MURALI MOHAN REDDY, DICKINSON PAUL

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  10. 10
    Testing multi-core processors

    Testing multi-core processors von Gala, Murali Mohan Reddy, Caty, Olivier Francis Cyrille, Ziaja, Thomas Alan, Dickinson, Paul

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  11. 11
    INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE

    INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE von WOODLING KEVIN D, ZIAJA THOMAS ALAN, MOLYNEAUX ROBERT F

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  12. 12
    TESTING MULTI-CORE PROCESSORS

    TESTING MULTI-CORE PROCESSORS von ZIAJA THOMAS ALAN, CATY OLIVIER FRANCIS CYRILLE, GALA MURALI MOHAN REDDY, DICKINSON PAUL JOHN

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  13. 13
    Enabling on-chip features via efuses

    Enabling on-chip features via efuses von Grohoski, Gregory F, Olson, Christopher H, Ziaja, Thomas Alan, Spracklen, Lawrence A

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  14. 14
    Enabling on-chip features via efuses

    Enabling on-chip features via efuses von ZIAJA THOMAS ALAN, SPRACKLEN LAWRENCE A, OLSON CHRISTOPHER H, GROHOSKI GREGORY F

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