Exploring sub-20nm FinFET design with predictive technology models von Sinha, Saurabh, Yeric, Greg, Chandra, Vikas, Cline, Brian, Cao, Yu

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A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software von Karthikeyan, M., Fox, S., Cote, W., Yeric, G., Hall, M., Garcia, J., Mitchell, B., Wolf, E., Agarwal, S.

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Special Section on the International Conference on Microelectronic Test Structures von Yeric, Greg

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Physically-based models for effective mobility and local-field mobility of electrons in MOS inversion layers von Shin, H., Yeric, G.M., Tasch, A.F., Maziar, C.M.

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Correlating models and silicon for improved parametric yield von Aitken, R, Yeric, G, Flynn, D

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Improved universal MOSFET electron mobility degradation models for circuit simulation von Yue, C., Agostinelli, V.M., Yeric, G.M., Tasch, A.F.

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Universal MOSFET hole mobility degradation models for circuit simulation von Agostinelli, V.M., Yeric, G.M., Tasch, A.F.

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Technology roadmaps and low power SoC design von Yeric, G.

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Degradation of insulators in Silicon Selective Epitaxial Growth (SEG) ambient von Bashir, R., Kim, S., Qadri, N., Jin, D., Neudeck, G.W., Denton, J.P., Yeric, G., Wu, K., Tasch, A.

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Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing von Karthikeyan, M., Gasasira, A., Fox, S., Yeric, G., Hall, M.

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A universal MOSFET mobility degradation model for circuit simulation von Yeric, G.M., Tasch, A.F., Banerjee, S.K.

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A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software von Karthikeyan, M., Fox, S., Cote, W., Yeric, G., Hall, M., Garcia, J., Mitchell, B., Wolf, E., Agarwal, S.

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Infrastructure for successful BEOL characterization and yield ramp at the 65 nm node and below von DeBord, J.R.D., Grice, T., Garcia, R., Yeric, G., Cohen, E., Sutandi, A., Garcia, J., Green, G.

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Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below von Yeric, G., Cohen, E., Garcia, J., Davis, K., Salem, E., Green, G.

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TDNVRAM/sup TM/: methodology and architecture of a nonvolatile-memory technology development testchip von Montanari, D., Deshazo, D., Yeric, G.

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