A 2 \times 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems von Takemoto, Takashi, Hayashi, Masato, Yoshimura, Chihiro, Yamaoka, Masanao

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A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines von OKU, Daisuke, TERADA, Kotaro, HAYASHI, Masato, YAMAOKA, Masanao, TANAKA, Shu, TOGAWA, Nozomu

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Overview of CMOS Annealing Machine von Yamaoka, Masanao

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A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing von Yamaoka, Masanao, Yoshimura, Chihiro, Hayashi, Masato, Okuyama, Takuya, Aoki, Hidetaka, Mizuno, Hiroyuki

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Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing von Yoshimura, Chihiro, Hayashi, Masato, Okuyama, Takuya, Yamaoka, Masanao

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STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions von Yamamoto, Kasho, Kawamura, Kazushi, Ando, Kota, Mertig, Normann, Takemoto, Takashi, Yamaoka, Masanao, Teramoto, Hiroshi, Sakai, Akira, Takamaeda-Yamazaki, Shinya, Motomura, Masato

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A 2 [Formula Omitted] 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems von Takemoto, Takashi, Hayashi, Masato, Yoshimura, Chihiro, Yamaoka, Masanao

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Adaptive Circuits for the 0.5-V Nanoscale CMOS Era von ITOH, Kiyoo, YAMAOKA, Masanao, OSHIMA, Takashi

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Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution von Hayashi, Masato, Yamaoka, Masanao, Yoshimura, Chihiro, Okuyama, Takuya, Aoki, Hidetaka, Mizuno, Hiroyuki

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Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM von Tega, N., Miki, H., Yamaoka, M., Kume, H., Toshiyuki Mine, Ishida, T., Yuki Mori, Yamada, R., Kazuyoshi Torii

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Binary optimization by momentum annealing von Okuyama, Takuya, Sonobe, Tomohiro, Kawarabayashi, Ken-Ichi, Yamaoka, Masanao

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Semiconductor CMOS Annealing Machine Accelerating Combinatorial Optimization Processing von YAMAOKA, Masanao

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Uncertain behaviours of integrated circuits improve computational performance von Yoshimura, Chihiro, Yamaoka, Masanao, Hayashi, Masato, Okuyama, Takuya, Aoki, Hidetaka, Kawarabayashi, Ken-ichi, Mizuno, Hiroyuki

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Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes von Sugie, Yuya, Yoshida, Yuki, Mertig, Normann, Takemoto, Takashi, Teramoto, Hiroshi, Nakamura, Atsuyoshi, Takigawa, Ichigaku, Minato, Shin-ichi, Yamaoka, Masanao, Komatsuzaki, Tamiki

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A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis von Yamaoka, M., Osada, K., Kawahara, T.

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1.3- \mu m Silicon Optical Switch Integrated With Germanium Photodiodes for Stable Operation von Suzuki, Takanori, Motoya, Toru, Yamaoka, Masanao, Kato, Takeshi, Aoki, Hidetaka, Tanaka, Shigehisa

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A CMOS Ising computer implemented by semiconductor circuits von Yamaoka, Masanao

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90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique von Yamaoka, M., Maeda, N., Shinozaki, Y., Shimazaki, Y., Nii, K., Shimada, S., Yanagisawa, K., Kawahara, T.

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組合せ最適化処理を加速する半導体CMOSアニーリングマシン von 山岡, 雅直

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A CMOS Annealing Machine to Solve Combinatorial Optimization Problems von YAMAOKA, Masanao

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