Reducing Critical Configuration Bits via Partial TMR for SEU Mitigation in FPGAs von Xiaoxuan She, Li, N.

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Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation von Xiaoxuan She, McElvain, K.S.

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SEU Tolerant Latch Based on Error Detection von Xiaoxuan She, Li, N., Tong, J.

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SEU Tolerant Memory Using Error Correction Code von Xiaoxuan She, Li, N., Jensen, D. W.

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Single event transient tolerant frequency divider von She, Xiaoxuan, Li, Ningxi

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SET Tolerant Dynamic Logic von Xiaoxuan She, Li, N., Erstad, D. O.

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Tunable SEU-Tolerant Latch von Xiaoxuan She, Li, N, Farwell, W D

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Single Event Transient Suppressor for Flip-Flops von Xiaoxuan She, Li, N, Carlson, R M, Erstad, D O

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Notice of Removal: FPGA Logic Block to Implement Resource-Efficient Multiplexers von She, Xiaoxuan, Li, N., Kaviani, A. Slarry

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Single event transient tolerant frequency divider von XIAOXUAN SHE, NINGXI LI

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Digital circuit evolution for scalability von Xiaoxuan She

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Channel allocation method based on data traffic mean square error von SHE XIAOXUAN

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Channel allocation method based on data traffic and interference intensity von SHE XIAOXUAN

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Hierarchical channel allocation method von SHE XIAOXUAN

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Channel allocation method based on interference relation matrix von SHE XIAOXUAN

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Channel allocation method based on interference signal power von SHE XIAOXUAN

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Preparation method of anti-radiation fault-tolerant trigger von SHE XIAOXUAN

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Self-adaptive evolution of complex logic circuits von Xiaoxuan She, Jinmei Lai

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Error correction anti-radiation circuit design method von SHE XIAOXUAN

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A radiation-resistant and fault-tolerant FPGA circuit design method for reducing sensitive configuration bits through local redundancy von SHE XIAOXUAN

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