LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion von Feng, Kunyu, Lun, Li, Wang, Xiaofeng, Cui, Xiaoxin

Volltext

An all integer-based spiking neural network with dynamic threshold adaptation von Zou, Chenglong, Cui, Xiaoxin, Feng, Shuo, Chen, Guang, Zhong, Yi, Dai, Zhenhui, Wang, Yuan

Volltext

A Comparative Study on the Performance and Security Evaluation of Spiking Neural Networks von Li, Yanjie, Cui, Xiaoxin, Zhou, Yihao, Li, Ying

Volltext

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates von Cui, Xiaole, Ma, Xiao, Lin, Qiujun, Li, Xiang, Zhou, Hang, Cui, Xiaoxin

Volltext

Toward a Lossless Conversion for Spiking Neural Networks with Negative‐Spike Dynamics von Zou, Chenglong, Cui, Xiaoxin, Chen, Guang, Jiang, Yuanyuan, Wang, Yuan

Volltext

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ) von Liao, Kai, Cui, Xiaoxin, Liao, Nan, Wang, Tian, Yu, Dunshan, Cui, Xiaole

Volltext

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias von Cui, Xiaole, Cui, Xiaoxin, Ni, Yewen, Miao, Min, Yufeng, Jin

Volltext

A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware von Zou, Chenglong, Cui, Xiaoxin, Kuang, Yisong, Liu, Kefei, Wang, Yuan, Wang, Xinan, Huang, Ru

Volltext

An Improved iMemComp OR Gate and its Applications in Logic Circuits von Wei, Feng, Cui, Xiaole, Cui, Xiaoxin

Volltext

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates von Cui, Xiaole, Ma, Ye, Wei, Feng, Cui, Xiaoxin

Volltext

Design of the RRAM-Based Polymorphic Look-Up Table Scheme von Cui, Xiaole, Li, Xiang, Zhang, Miaomiao, Cui, Xiaoxin

Volltext

A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model von Liu, Kefei, Cui, Xiaoxin, Zhong, Yi, Kuang, Yisong, Wang, Yuan, Tang, Huajin, Huang, Ru

Volltext

Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array von Cui, Xiaole, Zhang, Miaomiao, Lin, Qiujun, Cui, Xiaoxin, Pang, Anqi

Volltext

Low power adiabatic logic based on FinFETs von Liao, Nan, Cui, XiaoXin, Liao, Kai, Ma, KaiSheng, Wu, Di, Wei, Wei, Li, Rui, Yu, DunShan

Volltext

Improving DFA attacks on AES with unknown and random faults von Liao, Nan, Cui, Xiaoxin, Liao, Kai, Wang, Tian, Yu, Dunshan, Cui, Xiaole

Volltext

Testing of 1TnR RRAM array with sneak path technique von Cui, Xiaole, Zhang, Qiang, Cui, Xiaoxin, Wang, Xinan, Kang, Jinfeng, Liu, Xiaoyan

Volltext

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology von WANG, Tian, CUI, Xiaoxin, LIAO, Kai, LIAO, Nan, CUI, Xiaole, YU, Dunshan

Volltext

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique von Wang, Tian, Cui, Xiaoxin, Ni, Yewen, Liao, Kai, Liao, Nan, Yu, Dunshan, Cui, Xiaole

Volltext

Key characterization factors of accurate power modeling for FinFET circuits von Ma, KaiSheng, Cui, XiaoXin, Liao, Kai, Liao, Nan, Wu, Di, Yu, DunShan

Volltext

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs von Liao, Kai, Cui, XiaoXin, Liao, Nan, Ma, KaiSheng, Wu, Di, Wei, Wei, Li, Rui, Yu, DunShan

Volltext