High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO von Tang, Chuan, Liu, Cang, Yuan, Luechao, Xing, Zuocheng

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Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map von Li, Zerun, Wang, Qinglin, Zhu, Yufei, Xing, Zuocheng

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Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router von Chaochao Feng, Zhonghai Lu, Jantsch, A., Minxuan Zhang, Zuocheng Xing

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Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm von Chen, Lirui, Xing, Zuocheng, Li, Yongzhong, Qiu, Shikai

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Low latency group‐sorted QR decomposition algorithm for larger‐scale MIMO systems von Chen, Lirui, Wang, Yu, Xing, Zuocheng, Qiu, Shikai, Wang, Qinglin, Li, Yongzhong

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Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems von Liu, Cang, Tang, Chuan, Xing, Zuocheng, Yuan, Luechao, Zhang, Yang

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High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes von Zhu, Yufei, Xing, Zuocheng, Li, Zerun, Zhang, Yang, Hu, Yifan

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A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems von Liu, Cang, Xing, Zuocheng, Yuan, Luechao, Tang, Chuan, Zhang, Yang

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An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture von Wang, Yu, Chen, Lirui, Liu, Cang, Xing, Zuocheng

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An Area-Efficient Hybrid Polar Decoder with Pipelined Architecture von Wang, Yu, Wang, Qinglin, Zhang, Yang, Qiu, Shikai, Xing, Zuocheng

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Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph von Zhu, Yufei, Xing, Zuocheng, Xue, Jinhui, Li, Zerun, Hu, Yifan, Zhang, Yang, Li, Yongzhong

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Deep learning-aided high-precision data detection for massive MU-MIMO systems von Yang, Sen, Li, Zerun, Wei, Jinhui, Xing, Zuocheng

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Approximate iteration detection and precoding in massive MIMO von Tang, Chuan, Tao, Yerong, Chen, Yancang, Liu, Cang, Yuan, Luechao, Xing, Zuocheng

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A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation von Luechao Yuan, Cang Liu, Chuan Tang, Shan Huang, Chattopadhyay, Anupam, Ascheid, Gerd, Zuocheng Xing

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Architecture and Implementation of a Reduced EPIC Processor von GAO, Jun, ZHANG, Minxuan, XING, Zuocheng, FENG, Chaochao

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Applying Partial Power-Gating to Direction-Sliced Network-on-Chip von Wang, Feng, Xing, Zuocheng, Tang, Xiantuo

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Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming von Yang, Xuejun, Yan, Xiaobo, Xing, Zuocheng, Deng, Yu, Jiang, Jiang, Du, Jing, Zhang, Ying

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FPGA Implementation for the Sigmoid with Piecewise Linear Fitting Method Based on Curvature Analysis von Li, Zerun, Zhang, Yang, Sui, Bingcai, Xing, Zuocheng, Wang, Qinglin

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An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors von Zhang, Chengyi, Zhou, Hongwei, Zhang, Minxuan, Xing, Zuocheng

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Approximate iteration detection with iterative refinement in massive MIMO systems von Tang, Chuan, Liu, Cang, Yuan, Luechao, Xing, Zuocheng

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