High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch von Wang, Xiaoguang, Xiao, Deyuan, Huang, J. P., Lee, Tzunghan, Zheng, Yuhong, Cao, Kanyu, Dong, Kaifeng, Jin, Fang

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An Innovative Method to Improve Model Accuracy by Implementing Multi-models Scheme for 28nm Node and Below von Cao, Qingchen, Li, Tianhui, Wang, Shuying, Xiao, Deyuan

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Challenges of 22 nm and beyond CMOS technology von Huang, Ru, Wu, HanMing, Kang, JinFeng, Xiao, DeYuan, Shi, XueLong, An, Xia, Tian, Yu, Wang, RunSheng, Zhang, LiangLiang, Zhang, Xing, Wang, YangYuan

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72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM von Wang, Xiaoguang, Li, Huihui, Zeng, Dinggui, Deng, Jiefang, Xiao, Deyuan, Zhao, Chao, Cao, Kanyu

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Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array von Tian, Chao, Sun, Jiabao, Ping, Yanlei, Wang, Naizheng, Han, Baodong, Liu, Zhao, Li, Yongjie, Meng, Jingheng, Sun, Hongbo, Wang, Guilei, Chu, Jian, Shao, Guangsu, Shen, Jie, Qiu, Yunsong, Park, Ted, Xiao, Deyuan, Yoo, Abraham, Zhao, Chao

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Planar split dual gate MOSFET von Xiao, DeYuan, Chen, Gary, Lee, Roger, Liu, Yung, Shen, ChiCheong

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TDDB improvement by optimized processes on metal–insulator–silicon capacitors with atomic layer deposition of Al2O3 and multi layers of TiN film structure von Kun, Peng, Biao, Wang, Deyuan, Xiao, Shengfen, Qiu, Lin, D C, Ping, Wu, Yang, S F

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A novel GAAC FinFET transistor： device analysis, 3D TCAD simulation, and fabrication von 肖德元 王曦 袁海江 俞跃辉 谢志峰 季明华

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Semiconductor structure and method for manufacturing same von Xiao, Deyuan

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Stacked neural device structure and manufacturing method thereof von Xiao, Deyuan

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Hazardous Chemicals Management von Xiao, Deyuan

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Central Gas and Chemical Supply Systems von Xiao, Deyuan

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Clean Room and Air Conditioning Systems von Xiao, Deyuan

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STORAGE UNIT AND PREPARATION METHOD THEREFOR, AND MEMORY AND PREPARATION METHOD THEREFOR von XIAO, Deyuan

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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR von XIAO, Deyuan

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STORAGE UNIT AND PREPARATION METHOD THEREFOR, AND MEMORY AND PREPARATION METHOD THEREFOR von XIAO, Deyuan

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SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME von XIAO, Deyuan

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MEMORY CELL AND MANUFACTURING METHOD THEREOF, AND MEMORY AND MANUFACTURING METHOD THEREOF von XIAO, Deyuan

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Stacked neural device structure and manufacturing method thereof von Xiao, Deyuan

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Semiconductor structure with a first lower electrode layer and a second lower electrode layer and method for manufacturing same von Zhang, Lixia, Xiao, Deyuan

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