An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory von Mao, Mengjie, Wen, Wujie, Zhang, Yaojun, Chen, Yiran, Li, Hai

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The Prospect of STT-RAM Scaling From Readability Perspective von Zhang, Yaojun, Wen, Wujie, Chen, Yiran

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FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency von Guo, Jie, Wen, Wujie, Hu, Jingtong, Wang, Danghui, Li, Hai, Chen, Yiran

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Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation von Hosseini, Fateme S., Meng, Fanruo, Yang, Chengmo, Wen, Wujie, Cammarota, Rosario

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PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method von Wen, Wujie, Zhang, Yaojun, Chen, Yiran, Wang, Yu, Xie, Yuan

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Secure and efficient general matrix multiplication on cloud using homomorphic encryption von Gao, Yang, Quan, Gang, Homsi, Soamar, Wen, Wujie, Wang, Liqiang

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Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache von Xunchao Chen, Khoshavi, Navid, DeMara, Ronald F., Jun Wang, Dan Huang, Wujie Wen, Yiran Chen

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Model Compression Hardens Deep Neural Networks: A New Perspective to Prevent Adversarial Attacks von Liu, Qi, Wen, Wujie

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Multi-level cell STT-RAM: is it realistic or just a dream? von Zhang, Yaojun, Zhang, Lu, Wen, Wujie, Sun, Guangyu, Chen, Yiran

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An Image Enhancing Pattern-Based Sparsity for Real-Time Inference on Mobile Devices von Ma, Xiaolong, Niu, Wei, Zhang, Tianyun, Liu, Sijia, Lin, Sheng, Li, Hongjia, Wen, Wujie, Chen, Xiang, Tang, Jian, Ma, Kaisheng, Ren, Bin, Wang, Yanzhi

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Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory von Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li

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State-restrict MLC STT-RAM designs for high-reliable high-performance memory system von Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen

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Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System von Yang, Chaofei, Liu, Beiye, Li, Hai, Chen, Yiran, Barnell, Mark, Wu, Qing, Wen, Wujie, Rajendran, Jeyavijayan

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M-Oscillating: Performance Maximization on Temperature-Constrained Multi-Core Processors von Sha, Shi, Wen, Wujie, Ren, Shaolei, Quan, Gang

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FlexLevel: A novel NAND flash storage system design for LDPC latency reduction von Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Li, Yiran Chen

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Thermal-constrained energy efficient real-time scheduling on multi-core platforms von Sha, Shi, Wen, Wujie, Chaparro-Baquero, Gustavo A., Quan, Gang

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TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations von Liu, Zihao, Mao, Mengjie, Liu, Tao, Wang, Xue, Wen, Wujie, Chen, Yiran, Li, Hai, Wang, Danghui, Pei, Yukui, Ge, Ning

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A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement von Eken, Enes, Zhang, Yaojun, Wen, Wujie, Joshi, Rajiv, Li, Helen, Chen, Yiran

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Improving AES Core Performance via an Advanced ASBUS Protocol von Yang, Xiaokun, Wen, Wujie, Fan, Ming

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STT-RAM reliability enhancement through ECC and access scheme optimization von Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen

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