On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs von Lixin Ge, Gamiz, F., Workman, G.O., Veeraraghavan, S.

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A surface potential-based compact model of n-MOSFET gate-tunneling current von Xin Gu, Ten-Lon Chen, Gildenblat, G., Workman, G.O., Veeraraghavan, S., Shapira, S., Stiles, K.

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PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations von Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.

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Physical noise modeling of SOI MOSFETs with analysis of the Lorentzian component in the low-frequency noise spectrum von Workman, G.O., Fossum, J.G.

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A process/physics-based compact model for nonclassical CMOS device and circuit design von Fossum, J.G., Ge, L., Chiang, M.-H., Trivedi, V.P., Chowdhury, M.M., Mathew, L., Workman, G.O., Nguyen, B.-Y.

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A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs von Wu, W., Xin Li, Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.

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A nonlinear body resistance model for accurate PD/SOI technology characterization von Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Watts, J.

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Physical modeling of temperature dependences of SOI CMOS devices and circuits including self-heating von Workman, G.O., Fossum, J.G., Krishnan, S., Pelella, M.M.

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A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance von Workman, G.O., Fossum, J.G.

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Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges von Jung-Suk Goo, Williams, R.Q., Workman, G.O., Qiang Chen, Sungjae Lee, Nowak, E.J.

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Dynamic effects in BTG/SOI MOSFETs and circuits due to distributed body resistance von Workman, G.O., Fossum, J.G.

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Multiple independent gate field effect transistor (MIGFET) - multi-fin RF mixer architecture, three independent gates (MIGFET-T) operation and temperature characteristics von Mathew, L., Yang Du, Kaipat, S., Sadd, M., Zavala, M., Stephens, T., Mora, R., Rai, R., Becker, S., Parker, C., Sing, D., Shimer, R., Sanez, J., Thean, A.V.Y., Prabhu, L., Moosa, M., Nguyen, B.Y., Mogah, J., Workman, G.O., Vandooren, A., Shi, Z., Chowdhury, M.M., Zhang, W., Fossum, J.G.

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ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET von Mathew, L., Sadd, M., Kalpat, S., Zavala, M., Stephens, T., Mora, R., Rai, R., Parker, C., Vasek, J., Sing, D., Shinier, R., Prabhu, L., Workman, G.O., Ablen, G., Shi, Z., Saenz, J., Min, B., Burnett, D., Nguyen, B.Y., Mogab, J., Chowdhury, M.M., Zhang, W., Fossum, J.G.

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Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel te... von Mathew, L., Sadd, M., Kalpat, S., Zavala, M., Stephens, T., Mora, R., Bagchi, S., Parker, C., Vasek, J., Sing, D., Shimer, R., Prabhu, L., Workman, G.O., Ablen, G., Shi, Z., Saenz, J., Min, B., Burnett, D., Nguyen, B.-Y., Mogab, J., Chowdhury, M.M., Zhang, W., Fossum, J.G.

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Physics-based compact modeling for nonclassical CMOS von Trivedi, V.P., Fossum, G., Mathew, L., Chowdhury, M.M., Zhang, W., Workman, G.O., Nguyen, B.-Y.

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Analysis and control of hysteresis in PD/SOI CMOS von Pelella, M.M., Fossum, J.G., Chiang, M.-H., Workman, G.O., Tretz, C.R.

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