A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS von Nishi, Yoshinori, Poulton, John W., Turner, Walker J., Chen, Xi, Song, Sanquan, Zimmer, Brian, Tell, Stephen G., Nedovic, Nikola, Wilson, John M., Dally, William J., Gray, C. Thomas

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LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update von Zhao, Jiawei, Dai, Steve, Venkatesan, Rangharajan, Zimmer, Brian, Ali, Mustafa, Liu, Ming-Yu, Khailany, Brucek, Dally, William J., Anandkumar, Anima

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Elastic Buffer Flow Control for On-Chip Networks von Michelogiannakis, G., Dally, W. J.

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The GPU Computing Era von Nickolls, John, Dally, William J

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A Novel High-Efficiency Three-Phase Multilevel PV Inverter With Reduced DC-Link Capacitance von Chen, Tuofei, Gu, Lei, Dally, William J., Rivas-Davila, Juan, Fox, John

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Evolution of the Graphics Processing Unit (GPU) von Dally, William J., Keckler, Stephen W., Kirk, David B.

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GPUs and the Future of Parallel Computing von Keckler, S. W., Dally, W. J., Khailany, B., Garland, M., Glasco, D.

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Reuse Distance-Based Probabilistic Cache Replacement von Das, Subhasis, Aamodt, Tor M., Dally, William J.

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Accelerating Chip Design With Machine Learning von Khailany, Brucek, Ren, Haoxing, Dai, Steve, Godil, Saad, Keller, Ben, Kirby, Robert, Klinefelter, Alicia, Venkatesan, Rangharajan, Zhang, Yanqing, Catanzaro, Bryan, Dally, William J.

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Darwin: A Genomics Coprocessor von Turakhia, Yatish, Bejerano, Gill, Dally, William J.

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm von Zimmer, Brian, Venkatesan, Rangharajan, Shao, Yakun Sophia, Clemons, Jason, Fojtik, Matthew, Jiang, Nan, Keller, Ben, Klinefelter, Alicia, Pinckney, Nathaniel, Raina, Priyanka, Tell, Stephen G., Zhang, Yanqing, Dally, William J., Emer, Joel S., Gray, C. Thomas, Keckler, Stephen W., Khailany, Brucek

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A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm von Keller, Ben, Venkatesan, Rangharajan, Dai, Steve, Tell, Stephen G., Zimmer, Brian, Sakr, Charbel, Dally, William J., Gray, C. Thomas, Khailany, Brucek

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A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors von GEBHART, Mark, JOHNSON, Daniel R, TARJAN, David, KECKLER, Stephen W, DALLY, William J, LINDHOLM, Erik, SKADRON, Kevin

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A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator von Poulton, John W., Wilson, John M., Turner, Walker J., Zimmer, Brian, Chen, Xi, Kudva, Sudhir S., Song, Sanquan, Tell, Stephen G., Nedovic, Nikola, Zhao, Wenxu, Sudhakaran, Sunil R., Gray, C. Thomas, Dally, William J.

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A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS von Poulton, J., Palmer, R., Fuller, A.M., Greer, T., Eyles, J., Dally, W.J., Horowitz, M.

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A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS von Nishi, Yoshinori, Poulton, John W., Turner, Walker J., Chen, Xi, Song, Sanquan, Zimmer, Brian, Tell, Stephen G., Nedovic, Nikola, Wilson, John M., Dally, William J., Gray, C. Thomas

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Research Challenges for On-Chip Interconnection Networks von Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W., Li-Shiuan Peh

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Energy Efficient On-Demand Dynamic Branch Prediction Models von Mohammadi, Milad, Han, Song, Atoofian, Ehsan, Baniasadi, Amirali, Aamodt, Tor M., Dally, William J.

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Champagne: Automated Whole-Genome Phylogenomic Character Matrix Method Using Large Genomic Indels for Homoplasy-Free Inference von Schull, James K, Turakhia, Yatish, Hemker, James A, Dally, William J, Bejerano, Gill

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Efficient Embedded Computing von Dally, W.J., Balfour, J., Black-Shaffer, D., Chen, J., Harting, R.C., Parikh, V., Park, J., Sheffield, D.

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