Electrical and Interfacial Characterization of Atomic Layer Deposited High- \kappa Gate Dielectrics on GaAs for Advanced CMOS Devices von Dalapati, G.K., Yi Tong, Wei-Yip Loh, Hoe Keat Mun, Byung Jin Cho

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Si tunnel transistors with a novel silicided source and 46mV/dec swing von Kanghoon Jeon, Wei-Yip Loh, Patel, P, Chang Yong Kang, Jungwoo Oh, Bowonder, A, Chanro Park, Park, C S, Smith, C, Majhi, P, Hsing-Huang Tseng, Jammy, R, Liu, Tsu-Jae King, Chenming Hu

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Performance Evaluation of In0.53Ga0.47As Esaki Tunnel Diodes on Silicon and InP Substrates von Thomas, Paul, Filmer, Matthew, Gaur, Abhinav, Pawlik, David J., Romanczyk, Brian, Marini, Enri, Rommel, Sean L., Majumdar, Kausik, Wei-Yip Loh, Man Hoi Wong, Hobbs, Chris, Bhatnagar, Kunal, Contreras-Guerrero, Rocio, Droopad, Ravi

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Contact Resistance Reduction to FinFET Source/Drain Using Novel Dielectric Dipole Schottky Barrier Height Modulation Method von Coss, B. E., Smith, C., Wei-Yip Loh, Majhi, P., Wallace, R. M., Kim, J., Jammy, R.

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Enhancement of the Flatband Modulation of Ni-Silicided Gates on Hf-Based Dielectrics von YANG, Jian-Jun, WANG, Xin-Peng, ZHU, Chun-Xiang, LI, Ming-Fu, YU, Hong-Yu, LOH, Wei-Yip, KWONG, Dim-Lee

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Work Function Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices von Xin Peng Wang, Eu-Jin Lim, A., Hong Yu Yu, Ming-Fu Li, Chi Ren, Wei-Yip Loh, Chun Xiang Zhu, Chin, A., Trigg, A.D., Yee-Chia Yeo, Biesemans, S., Guo-Qiang Lo, Dim-Lee Kwong

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Raman spectroscopy studies of dopant activation and free electron density of In0.53Ga0.47As via sulfur monolayer doping von Kort, Kenneth R., Hung, P. Y., Lysaght, Patrick D., Loh, Wei-Yip, Bersuker, Gennadi, Banerjee, Sarbajit

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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate von Se-Hoon Lee, Majhi, P., Ferrer, D. A., Pui-Yee Hung, Huang, J., Oh, J., Wei-Yip Loh, Sassman, B., Byoung-Gi Min, Hsing-Huang Tseng, Harris, R., Bersuker, G., Kirsch, P. D., Jammy, R., Banerjee, S. K.

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Work Function Tuning and Material Characteristics of Lanthanide-Incorporated Metal Nitride Gate Electrodes for NMOS Device Applications von Ren, C., Chan, D.S.H., Li, M.-F., Loh, W.-Y., Balakumar, S., Tung, C.H., Balasubramanian, N., Kwong, D.-L.

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Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation von Wei-Yip Loh, Etienne, H., Coss, B., Ok, I., Turnbaugh, D., Spiegel, Y., Torregrosa, F., Banti, J., Roux, L., Pui-Yee Hung, Jungwoo Oh, Sassman, B., Radar, K., Majhi, P., Hsing-Huang Tseng, Jammy, R.

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Impact of interfacial layer control using Gd2O3 in HfO2 gate dielectric on GaAs von Dalapati, Goutam Kumar, Tong, Yi, Loh, Wei Yip, Mun, Hoe Keat, Cho, Byung Jin

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Strained Si/SiGe Channel With Buried [Formula Omitted] for Improved Drivability, Gate Stack Integrity and Noise Performance von Wei-Yip Loh, Wei-Yip Loh, Hui Zang, Hui Zang, Hoon-Jung Oh, Hoon-Jung Oh, Kyu-Jin Choi, Kyu-Jin Choi, Hoai Son Nguyen, Hoai Son Nguyen, Guo-Qiang Lo, Guo-Qiang Lo, Byung Jin Cho, Byung Jin Cho

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Electrical and Interfacial Characterization of Atomic Layer Deposited High- [kappa] Gate Dielectrics on GaAs for Advanced CMOS Devices von Dalapati, G.K, Yi Tong, Yi Tong, Wei-Yip Loh, Wei-Yip Loh, Hoe Keat Mun, Hoe Keat Mun, Byung Jin Cho, Byung Jin Cho

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Junction contact materials and interfaces in Si channel devices von Loh, Wei-Yip, Coss, Brian

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Raman scattering study of LO phonon–plasmon coupled modes in p-type InGaAs von Cuscó, Ramon, Domènech-Amador, Núria, Hung, P.Y., Loh, Wei-Yip, Droopad, R., Artús, Luis

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Dielectric dipole mitigated Schottky barrier height tuning using atomic layer deposited aluminum oxide for contact resistance reduction von Coss, Brian E., Loh, Wei-Yip, Carlo Floresca, Herman, Kim, Moon J., Majhi, Prashant, Wallace, Robert M., Kim, Jiyoung, Jammy, Raj

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Determination of Free Electron Density in Sequentially Doped InxGa1-xAs by Raman Spectroscopy von Kort, Kenneth R., Hung, P.Y., Loh, Wei-Yip, Bersuker, Gennadi, Banerjee, Sarbajit

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Thermal Immune NiGermanide for High Performance Ge MOSFETs on Ge-on- Si Substrate Utilizing [Formula Omitted] Alloy von Ying-Ying Zhang, Ying-Ying Zhang, Jungwoo Oh, Jungwoo Oh, In-Shik Han, In-Shik Han, Zhun Zhong, Zhun Zhong, Shi-Guang Li, Shi-Guang Li, Soon-Yen Jung, Soon-Yen Jung, Kee-Young Park, Kee-Young Park, Hong-Sik Shin, Hong-Sik Shin, Won-Ho Choi, Won-Ho Choi, Hyuk-Min Kwon, Hyuk-Min Kwon, Wei-Yip Loh, Wei-Yip Loh, Majhi, P, Jammy, R, Hi-Deok Lee, Hi-Deok Lee

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STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity von Majumdar, Kausik, Vivekanand, Saikumar, Huffman, Craig, Matthews, Ken, Tat Ngai, Chien Hao Chen, Baek, Rock Hyun, Wei Yip Loh, Rodgers, Martin, Stamper, Harlan, Gausepohl, Steven, Chang Yong Kang, Hobbs, Chris, Kirsch, Paul D.

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Mapping Defect Density in MBE Grown Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics von Majumdar, Kausik, Thomas, Paul, Wei-Yip Loh, Pui-Yee Hung, Matthews, Ken, Pawlik, David, Romanczyk, Brian, Filmer, Matthew, Gaur, Abhinav, Droopad, Ravi, Rommel, Sean L., Hobbs, Chris, Kirsch, Paul D.

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