On testability of differential split-level CMOS circuits von Aziz, S.M., Waller, W.A.J.

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A digital engineering curriculum with integrated, Windows-based EDA tools von Walczowski, L.T., Dimond, K.R., Waller, W.A.J.

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Java servlet technology for analogue module generation von Walczowski, L.T., Waller, W.A.J.

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Device sizing for silicon compilers using CSL von Walczowski, L.T., Smith, M.H., Waller, W.A.J., Howard, D.

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O/sup 2/ADL: an object-oriented analog VLSI design language von Shi, K., Walczowski, L.T., Nalbantis, D., Waller, W.A.J.

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Multiple server WWW-based synthesis of VLSI circuits von Nalbantis, D., Walczowski, L.T., Waller, W.A.J.

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A method for sizing transistors in CMOS op-amps von Smith, M.H., Walczowski, L.T., Waller, W.A.J., Howard, D.

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A high-speed two's complement multiplier using differential split-level CMOS von Aziz, S.M., Waller, W.A.J.

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Analogue layout generation by World Wide Web server-based agents von Walczowski, L.T., Nalbantis, D., Waller, W.A.J., Shi, K.

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A new bipolar op-amp IC synthesis approach von Shi, K., Walczowski, L.T., Waller, W.A.J., Nalbantis, D.

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Rapid layout synthesis for analog VLSI von Walczowski, L.T., Waller, W.A.J., Nalbantis, D., Shi, K.

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