The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer von FUKASE, Naohisa, MIURA, Yasuyuki, WATANABE, Shigeyoshi, RAHMAN, M.M. HAFIZUR

Volltext

Design Technology of Stacked-Type Chain PRAM von Kato, Sho, Watanabe, Shigeyoshi

Volltext

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram von NINOMIYA, Hiroshi, KOBAYASHI, Manabu, WATANABE, Shigeyoshi

Volltext

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs von NINOMIYA, Hiroshi, KOBAYASHI, Manabu, MIURA, Yasuyuki, WATANABE, Shigeyoshi

Volltext

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs von KOBAYASHI, Manabu, NINOMIYA, Hiroshi, MIURA, Yasuyuki, WATANABE, Shigeyoshi

Volltext

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs von KOBAYASHI, Manabu, NINOMIYA, Hiroshi, WATANABE, Shigeyoshi

Volltext

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram von NINOMIYA, Hiroshi, KOBAYASHI, Manabu, WATANABE, Shigeyoshi

Volltext

Design Technology of Stacked Type DTMOS von Hiroshima, Yu, Kodama, Takahiro, Watanabe, Shigeyoshi

Volltext

An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance von Miura, Yasuyuki, Shimozono, Kentaro, Fukase, Naohisa, Watanabe, Shigeyoshi, Matoyama, Kazuya

Volltext

Adaptive Routing Algorithms and Implementation for TESH Network von Miura, Yasuyuki, Kaneko, Masahiro, M. Hafizur Rahman, M., Watanabe, Shigeyoshi

Volltext

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs von Kobayashi, Manabu, Ninomiya, Hiroshi, Miura, Yasuyuki, Watanabe, Shigeyoshi

Volltext

Link-sharing method of buffer in direct-connection network von Fukase, N., Miura, Y., Watanabe, S.

Volltext

FOREWORD von WATANABE, Shigeyoshi

Volltext

FOREWORD von WATANABE, Shigeyoshi

Volltext

Design technology of stacked NAND-type FeRAM with two-transistor-type memory cell von Sugano, Koichi, Watanabe, Shigeyoshi

Volltext

Design Technology of stacked NAND type 1-transistor FeRAM von Sugano, Koichi, Watanabe, Shigeyoshi

Volltext

A Car-Steering Model Based on an Adaptive Neuro-Fuzzy Controller von Amor, Mohamed Anis Ben, Oda, Takeshi, Watanabe, Shigeyoshi

Volltext

Study of stacked NOR type MRAM for universal memory von Tamai, Shoto, Watanabe, Shigeyoshi

Volltext

Design methodology for system LSI with TIS (trench-isolated transistor using sidewall gate) von Watanabe, Shigeyoshi

Volltext

Study of stacked type logic LSI with fabrication technology of 3D NAND flash memory von Suzuki, Fumiya, Watanabe, Shigeyoshi

Volltext