Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture von KISHIMOTO, Takashi, TAKAHASHI, Wataru, WAKABAYASHI, Kazutoshi, OCHI, Hiroyuki

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Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing von KONOURA, Hiroaki, ALNAJJAR, Dawood, MITSUYAMA, Yukio, SHIMADA, Hajime, KOBAYASHI, Kazutoshi, KANBARA, Hiroyuki, OCHI, Hiroyuki, IMAGAWA, Takashi, WAKABAYASHI, Kazutoshi, HASHIMOTO, Masanori, ONOYE, Takao, ONODERA, Hidetoshi

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Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor von TOI, Takao, OKAMOTO, Takumi, AWASHIMA, Toru, WAKABAYASHI, Kazutoshi, AMANO, Hideharu

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Design Space Exploration Acceleration Through Operation Clustering von Schafer, Benjamin Carrion, Wakabayashi, Kazutoshi

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FOREWORD von WAKABAYASHI, Kazutoshi

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Fixed Point Data Type Modeling for High Level Synthesis von SCHAFER, Benjamin CARRION, IGUCHI, Yusuke, TAKAHASHI, Wataru, NAGATANI, Shingo, WAKABAYASHI, Kazutoshi

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High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor von Toi, Takao, Nakamura, Noritsugu, Kato, Yoshinosuke, Awashima, Toru, Wakabayashi, Kazutoshi

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FOREWORD von WAKABAYASHI, Kazutoshi

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Divide and conquer high-level synthesis design space exploration von Schafer, Benjamin Carrion, Wakabayashi, Kazutoshi

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Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation von Hashimoto, Masanori, Bai, Xu, Banno, Naoki, Tada, Munehiro, Sakamoto, Toshitsugu, Yu, Jaehoon, Doi, Ryutaro, Onodera, Hidetoshi, Imagawa, Takashi, Ochi, Hiroyuki, Wakabayashi, Kazutoshi, Mitsuyama, Yukio, Sugibayashi, Tadahiko

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Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars von Ochi, Hiroyuki, Yamaguchi, Kosei, Fujimoto, Tetsuaki, Hotate, Junshi, Kishimoto, Takashi, Higashi, Toshiki, Imagawa, Takashi, Doi, Ryutaro, Tada, Munehiro, Sugibayashi, Tadahiko, Takahashi, Wataru, Wakabayashi, Kazutoshi, Onodera, Hidetoshi, Mitsuyama, Yukio, Yu, Jaehoon, Hashimoto, Masanori

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CODES+ISSS 2009 guest editors’ introduction von Rosenstiel, Wolfgang, Wakabayashi, Kazutoshi

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Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture von Hihara, Hiroki, Iwasaki, Akira, Hashimoto, Masanori, Ochi, Hiroyuki, Mitsuyama, Yukio, Onodera, Hidetoshi, Kanbara, Hiroyuki, Wakabayashi, Kazutoshi, Sugibayashi, Tadahiko, Takenaka, Takashi, Hada, Hiromitsu, Tada, Munehiro, Miyamura, Makoto, Sakamoto, Toshitsugu

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C-based SoC design flow and EDA tools: an ASIC and system vendor perspective von Wakabayashi, K., Okamoto, T.

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Use of High-Level Synthesis to Generate Hardware from Software von Wakabayashi, Kazutoshi

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Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing von Alnajjar, Dawood, Konoura, Hiroaki, Mitsuyama, Yukio, Shimada, Hajime, Kobayashi, Kazutoshi, Kanbara, Hiroyuki, Ochi, Hiroyuki, Imagawa, Takashi, Noda, Shinichi, Wakabayashi, Kazutoshi, Hashimoto, Masanori, Onoye, Takao, Onodera, Hidetoshi

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Fixed Point Data Type Modeling for High Level Synthesis : Circuits and Design Techniques for Advanced Large Scale Integration von SCHAFER, Benjamin Carrion, IGUCHI, Yusuke, TAKAHASHI, Wataru, NAGATANI, Shingo, WAKABAYASHI, Kazutoshi

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Use of High-Level Synthesis to Generate Hardware from Software: Another Alternative General-Purpose Program-Executing Mechanism to the CPU von WAKABAYASHI, Kazutoshi

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High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor von Toi, Takao, Nakamura, Noritsugu, Kato, Yoshinosuke, Awashima, Toru, Wakabayashi, Kazutoshi

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Wire congestion aware synthesis for a dynamically reconfigurable processor von Toi, T, Okamoto, T, Awashima, T, Wakabayashi, K, Amano, H

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