Lithography aware critical area estimation and yield analysis von Vijayakumar, P., Suresh, V. B., Kundu, S.

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Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance von Vijayakumar, Priyamvada, Narayanan, Pritish, Koren, Israel, Krishna, C Mani, Moritz, C Andras

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Biased Voting for Improved Yield in Nanoscale Fabrics von Khan, M. M. U., Narayanan, P., Vijayakumar, P., Koren, I., Krishna, C. M., Moritz, C. A.

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On lithography aware metal-fill insertion von Suresh, V. B., Kumar, P. V., Kundu, S.

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On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements von Suresh, V. B., Vijayakumar, P., Kundu, S.

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3-D integration requirements for hybrid nanoscale-CMOS fabrics von Panchapakeshan, P., Vijayakumar, P., Narayanan, P., Chi On Chui, Koren, I., Moritz, C. A.

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Towards efficient on-chip sensor interconnect architecture for multi-core processors von Phanibhushana, B, Vijayakumar, P, Shabadi, P, Prabhu, G, Kundu, S

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Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics von Vijayakumar, Priyamvada, Narayanan, Pritish, Koren, Israel, Mani Krishna, C., Moritz, Csaba Andras

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Nanoscale Application Specific Integrated Circuits von Narayanan, Pritish, Kina, Jorge, Panchapakeshan, Pavan, Vijayakumar, Priyamvada, Shin, Kyeong-Sik, Rahman, Mostafizur, Leuchtenburg, Michael, Koren, Israel, Chui, Chi On, Moritz, Csaba Andras

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