Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches von Nikolos, D., Verges, H.T., Vazaios, A., Voulgaris, S.

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Efficient fault tolerant cache memory design von Verges, H.T., Nikolos, D.

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Results and Limits of Time-Division Multiplexing for the BICEP Array High-Frequency Receivers von Fatigoni, S., Ade, P. A. R., Ahmed, Z., Amiri, M., Barkats, D., Thakur, R. Basu, Bischoff, C. A., Beck, D., Bock, J. J., Buza, V., Cheshire, J., Connors, J., Cornelison, J., Crumrine, M., Cukierman, A. J., Denison, E. V., Dierickx, M. I., Duband, L., Eiben, M., Filippini, J. P., Fortes, A., Gao, M., Giannakopoulos, C., Goeckner-Wald, N., Goldfinger, D. C., Grayson, J. A., Grimes, P. K., Hall, G., Halal, G., Halpern, M., Hand, E., Harrison, S. A., Handerson, S., Hildebrandt, S. R., Hilton, G. C., Hubmayr, J., Hui, H., Irwin, K. D., Kang, J. H., Karkare, K. S., Kefeli, S., Kovac, J. M., Kuo, C. L., Lau, K., Lennox, A., Liu, T., Megerian, K. G., Miller, O. Y., Minutolo, L., Moncelsi, L., Nakato, Y., Nguyen, H. T., O’Brient, R., Palladino, S., Petroff, M. A., Polish, A., Prouve, T., Pryke, C., Racine, B., Reintsema, C. D., Romand, T., Salatino, M., Schillaci, A., Schmitt, B. L., Singari, B., Soliman, A., St.Germaine, T., Steiger, A., Steinbach, B., Sudiwala, R., Thompson, K. L., Tsai, C., Tucker, C., Turner, A. D., Umiltà, C., Vèrges, C., Wandui, A., Weber, A. C., Wiebe, D. V., Willmert, J., Wu, W. L. K., Yang, E., Young, E., Yu, C., Zeng, L., Zhang, C., Zhang, S.

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