Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells von Vianello, E., Driussi, F., Arreghini, A., Palestri, P., Esseni, D., Selmi, L., Akil, N., van Duuren, M.J., Golubovic, D.S.

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Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells von Arreghini, A., Driussi, F., Vianello, E., Esseni, D., van Duuren, M.J., Golubovic, D.S., Akil, N., van Schaijk, R.

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Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays von Vianello, E., Driussi, F., Esseni, D., Selmi, L., Widdershoven, F., van Duuren, M.J.

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New Charge Pumping model for the analysis of the spatial trap distribution in the nitride layer of SONOS devices von Arreghini, A., Driussi, F., Esseni, D., Selmi, L., van Duuren, M.J., van Schaijk, R.

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Defect generation statistics in thin gate oxides von Ielmini, D., Spinelli, A.S., Lacaita, A.L., van Duuren, M.J.

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Experimental characterization of statistically independent defects in gate dielectrics-part I: description and validation of the model von Driussi, F., Widdershoven, F., Esseni, D., Selmi, L., van Duuren, M.J.

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Experimental characterization of statistically independent defects in gate dielectrics-part II: experimental results on flash memory arrays von Driussi, F., Widdershoven, F., Esseni, D., Selmi, L., van Duuren, M.J.

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Impact of correlated generation of oxide defects on SILC and breakdown distributions von Ielmini, D., Spinelli, A.S., Lacaita, A.L., van Duuren, M.J.

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Impact of Device Layout and Annealing Process During the Passivation of Interface States in Presence of Silicon Nitride Layers von Driussi, F., Selmi, L., Akil, N., van Duuren, M.J., van Schaijk, R.

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Characterization and modeling of long term retention in SONOS non volatile memories von Arreghini, A., Akil, N., Driussi, F., Esseni, D., Selmi, L., van Duuren, M.J.

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Long term charge retention dynamics of SONOS cells von Arreghini, A., Akil, N., Driussi, F., Esseni, D., Selmi, L., van Duuren, M.J.

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On the passivation of interface states in SONOS test structures: impact of device layout and annealing process von Driussi, F., Selmi, L., Akil, N., van Duuren, M.J., van Schaijk, R.

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Vertical poly-Si select pn-diodes for emerging resistive non-volatile memories von Golubović, D.S., Miranda, A.H., Akil, N., van Schaijk, R.T.F., van Duuren, M.J.

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Experimental Extraction of the Charge Centroid and of the Charge Type in the P/E Operation of Sonos Memory Cells von Arreghini, A., Driussi, F., Esseni, D., Selmi, L., van Duuren, M.J., van Schaijk, R.

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Does Multi-Trap Assisted Tunneling explain the oxide thickness dependence of the Statistics of SILC in FLASH Memory Arrays? von Vianello, E., Driussi, F., Esseni, D., Selmi, L., van Duuren, M.J., Widdershoven, F.

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Smart SQUIDs based on relaxation oscillation SQUIDs von van Duuren, M.J., Brons, G.C.S., Flokstra, J., Rogalia, H.

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Double relaxation oscillation superconducting quantum interference devices with gradiometric layout von van Duuren, M. J., Brons, G. C. S., Adelerhof, D. J., Flokstra, J., Rogalla, H.

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A 1-MHz low noise preamplifier based on double relaxation oscillation SQUIDs von Hamster, A.W., van Duuren, M.J., Brons, G.C.S., Flokstra, J., Rogalla, H.

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Low input coil inductance SQUIDs for cryogenic current comparator applications von Sese, J., Camon, A., Rillio, C., Hiddink, M.G.H., Vargas, L., Van Duuren, M.J., Brons, G.C.S., Flokstra, J., Rogalla, H., Rietveld, G.

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A comparative study of characterization techniques for oxide reliability in flash memories von Ielmini, D., Spinelli, A.S., Lacaita, A.L., van Duuren, M.J.

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